MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints

Feng, Guangsheng; Feng, Guorui; Wu, Ning; Zhou, Lei; Liu, Jing

doi:10.1587/elex.13.20160082

Cited by 6 publications

(8 citation statements)

References 10 publications

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“…Moreover, the submatrix sum of quantities like heat, power, and power density considered in [5], [11], and [14] respectively alone cannot account for the degree of hotness of a region. Work done in [15] proposes a 3D MSP cube model for the thermal aware mapping of 3D NOC architecture. Also utilizing a genetic algorithm approach, it achieves improvements in temperature deviation, power, and delay.…”

Section: Related Workmentioning

confidence: 99%

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An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

Choudhury

Pradhan

2020

IEEE Access

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Since hotspots and temperature gradients are reliability and performance-critical issues in processors, thermal awareness finds a vital place in the processor design cycle. Incorporating thermal awareness at the level of physical design, this work proposes a new, fast, and efficient thermal aware placement algorithm called the Thermal Aware Matrix Placement Optimizer (TAMPO) for gate arrays. The algorithm TAMPO is composed of the following components: an improved heat diffusion aware cell arrangement technique called the Initial Matrix Generator (IMaGe), a unique stochastic thermal model based on a thermally improved interpretation of the well known Matrix Synthesis Problem (MSP) and a Simulated Annealing (SA) engine for finding the global optimum solution. TAMPO targets to reduce the peak temperature while maintaining improved values of temperature gradients and the standard deviation in cell temperature with respect to the average chip temperature. This work also presents a methodology, the Co-optimized TAMPO, which extends the concept of TAMPO to simultaneously optimize the thermal attributes and the wirelength of a chip. The proposed algorithms realize a placement in matrix arrangement and upon experimentation on the ISCAS89 benchmark circuits encouraging results have been obtained.

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Section: Related Workmentioning

confidence: 99%

“…The thermal metrics of the Simple Approximation based, the Hotspot tool based and the proposed TAMPO placement algorithms differ from each other in order of magnitude and dimension. The thermal metric has been normalized in (15)…”

Section: Cost Functionmentioning

confidence: 99%

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

Choudhury

Pradhan

2020

IEEE Access

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“…Thermalaware floorplanning methods for VLSI have been proposed [3,4,5,6,7,8,9]. Thermal-aware 3D network-on-chip (NoC) designs have been proposed [10,11]. Related to the thermal placement of 3D ICs, thermal through-silicon-via (TSV) optimization [12,13,14,15,16] and thermal floor plans [17,18,19,20,21,22,23,24,25,26] have been presented.…”

Section: Introductionmentioning

confidence: 99%

Thermal placement on PCB of components including 3D ICs

Satomi

Hachiya

Kanamoto

et al. 2020

IEICE Electron. Express

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In this letter, we propose a method for optimizing the thermal placement of heat and non-heat generating electronic components on a printed circuit board (PCB). Use a genetic algorithm to optimize the maximum temperature of the PCB and the total wire length between components. In the case that chips stacked in 3D ICs are reconfigurable, each chip construction of 3D ICs is also changed simultaneously. The temperature of each component is obtained by circuit simulation using a simple thermal circuit model. The experimental results demonstrate that the placement of components can be optimized well for lowering the maximum temperature with shorter wire lengths.

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“…Some are based on heuristic algorithms, such as genetic algorithm (GA), Simulated Annealing algorithm (SA), Particle Swarm algorithm (PS) and so on [3,4,5]. The others are based on specialized algorithms for NoC mapping [6,7,8].…”

Section: Introductionmentioning

confidence: 99%

An efficient energy and thermal-aware mapping for regular network-on-chip

Liu

Zhu

et al. 2017

IEICE Electron. Express

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Chip temperature and energy consumption become one of the most critical design issues with technology scaling to nanometre-scale, especially for NoC systems with large number of cores and shrunken core size. To balance the temperature and energy consumption on NoC-based multi-cores system, this paper proposes an efficient NoC mapping approach in which the hyper-heuristic algorithm based on genetic operators (HAGO) is the core of this approach. Compared to simulated annealing algorithm and genetic algorithm, HAGO demonstrates a faster convergence speed and excellent stability. Experimental results show that our proposed mapping approach can make a better balance between energy consumption and temperature, which reduces the peak temperature from 365.2 K to 352 K and only increases the energy consumption by 1.12%.

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MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints

Cited by 6 publications

References 10 publications

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

Thermal placement on PCB of components including 3D ICs

An efficient energy and thermal-aware mapping for regular network-on-chip

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