Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

Abstract

International audienceThis paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness

Electrical models of through silicon Vias and silicon‐based devices for millimeter‐wave application

“…Therefore, merging several active silicon FIGURE 13 Layout arrangement of the proposed single-interposer wideband filter: A, prospective view and B, side view FIGURE 14 Structure schematic of proposed LPF FIGURE 15 Schematic cross-sectional view of the monolithic 3D TSV coreless transformer in a silicon substrate FIGURE 16 The 3-D view of SIW based on the DC-TSV array parts into a single package leads to denser heat fluxes in the final stack, which cause self-heating issues. 47 The total power resulting from Joule effect in the transistors and interconnects may contribute to a strong increase of the global temperature of the chip. These thermal issues directly impact the reliability of integrated circuits.…”

“…Limitations in operating temperature are then fixed on products, according to the application, for example 85 C for memory and 120 C for processors chip. 47 As for the mmW applications of TSV-based 3D IC, the high power density exacerbates the thermal issues and results in very high temperature, which in turn degrades the performance of both transistors and interconnects. Additionally, the unintentional variance in the voltage drops associated with the temperature rise has to be considered especially with the lowering supply voltage and the reducing noise margin; otherwise, it may prevent the transistors from switching states and causes circuit failures.…”

“…With the rapid development of semiconductor technologies, the characteristic dimension of TSV‐based 3D ICs is reduced persistently, resulting into prominent expansion of the integration scale. Therefore, merging several active silicon parts into a single package leads to denser heat fluxes in the final stack, which cause self‐heating issues . The total power resulting from Joule effect in the transistors and interconnects may contribute to a strong increase of the global temperature of the chip.…”

“…These thermal issues directly impact the reliability of integrated circuits. Limitations in operating temperature are then fixed on products, according to the application, for example 85°C for memory and 120°C for processors chip …”

Effectiveness of thermal redistribution layer in cooling of 3D ICs

“…The second method uses the electro‐thermal duality to produce thermal network, which is solved through circuit analysis method. The FEA method traditionally exhibits high accuracy with experimental results, 23‐25 but the simulation process typically requires a long time and has certain requirements on the simulation environment. The large‐scale FEA will be limited by the computing speed and memory of the computer 26,27 .…”