The kinetics of formation of both fast and slow states at the Si-SiO2 interface during avalanche injection is carefully examined on Al gate, wet oxide metal-oxide-silicon capacitors. They are both found to approach exponentially a saturation value. The annealing behavior of fast and slow states is examined by means of isochronal heat treatments. They can be annihilated at temperatures lower than 600 °K with similar activation energies. Correlations between slow and fast states are discussed. The instability of flatband voltage after avalanche injection due to the presence of slow states is characterized at various temperatures and electric fields. A process involving thermal activated hopping (Continuous Time Random Walk Model) among the slow states may be invoked in order to explain the experimental data.
Thermal analysis is essential in 3D-IC technology due to the reduced footprint and higher power densities compared to conventional 2D packaging [1]. Compact thermal models (CTM) are being developed for fast evaluation of the thermal distribution in the 3D packages. The CTM discussed in this paper is based on the Green's function theory and exploits convolution and fast Fourier transform to compute the temperature profiles starting from matrices storing the power dissipation densities (power maps) and the temperature responses to hot spots. Detailed accuracy assessments are presented for the grid size and for the number of images to be considered for an accurate modelling of the lateral insulating boundary conditions. A two dies stack case study is also analysed showing good agreement with the finite element model results (error less than 0.5%). Finally, the algorithm computational time is discussed indicating a behaviour where N is the number of elements in the matrices.
A thorough thermal analysis of integrated circuits (ICs) is essential to prevent temperature driven reliability issues, which might cause the failure of microelectronic devices. The classical analysis approach is based on finite element methods (FEM). However, in the last decades, other computational methodologies have been developed with the aim to obtain results more quickly and at a reasonable accuracy. In this paper, a transient fast thermal model (TFTM) methodology for 3D-ICs based on 3D-convolution and fast Fourier transform is presented. This methodology allows to quickly and accurately predict the temporal evolution of the chip temperature distribution, due to power dissipation that can be non-uniform both in time and space, in all tiers of the 3D package.In the first part of the paper the computational methodology is derived and described. Next, results are presented and validated with respect to conventional FEM simulations, showing good accuracy and computational time reduction. A realistic case, wherein different load switching scenarios are compared for a commercial floor-plan, is analyzed as an example of the applicability of the presented methodology. The speed of this algorithm, based on 3D-convolution, is compared with the one of previous work based on 2D-convolution and subseq uent time superposition.
Electron avalanche injection is performed at various temperatures on Al gate, wet oxide metal-oxide-semiconductor capacitors. The observed behavior of the flatband voltage shift versus injected charge is well represented by a phenomenological model which includes the buildup of positively charged defects at the Si-SiO2 interface, their annealing, and their neutralization by ’’trapped’’ electrons. At high temperatures (T≳350 °K) annealing is very efficient, while for T≲250 °K the positive charge is quickly neutralized. Thus the ’’turn around’’ is observable at room temperature only. The role of trivalent silicon defects and of Si-H bonds is discussed.
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