The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D-ICs. Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multi-scale strategy whose core is constituted by a highly resolved, convolution based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite element method results shows good accuracy. An error metric, to estimate a priori the need to include the package impact on top of the convolution based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this work. Index Terms-Convolution, Electronic packaging thermal management, Fast thermal model.
I. INTRODUCTIONIGH temperatures and high spatial and/or temporal temperature gradients represent a significant issue for the design and the fabrication of performant and reliable integrated circuits (ICs) [1]. Thermal issues are further exacerbated in 3D systems where active components are stacked on top of each other. These issues are not only due to the increased power density dissipated over the same area available for cooling, but also to the use of adhesives with low thermal conductivity for the vertical integration of the electronic components and to the reduced lateral spreading in the thinned Si chips.Accurate thermal analysis of 3D-ICs is, therefore, crucial to This paragraph of the first footnote will contain the date on which you submitted your paper for review.