Thermal-Aware Test Data Compression Using Dictionary Based Coding

High temperature occurs in testing of complex System-on-Chip designs and it may become a critical concern to be carefully taken into account with continual development in Very Large Scale Integration technology. Peak temperature significantly affects the reliability and the performance of the chip. So it is essential to minimize the peak temperature of the chip. Heat generation by power consumption and heat dissipation to the surrounding blocks are the two prominent factors for the peak temperature. Power consumption can be minimized by a careful mapping of don't cares in precomputed test set. However, it does not provide the solution to peak temperature minimization because the non-uniformity in spatial power distribution may create localized heating event called "hotspot." The peak temperature on the hotspot is minimized by Genetic Algorithm-based don't care filling technique that reduces the non-uniformity in spatial power distribution within the circuit under test while maintaining the overall power consumption at a lower level. Experimental results on ISCAS89 benchmark circuits demonstrate that 6%-28% peak temperature reduction can be achieved.

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“…Thermal simulation was used to estimate the power and temperature distribution across the block. The thermal simulation 28 steps are as follows:…”

Section: Resultsmentioning

confidence: 99%

Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

Arulmurugan¹,

Murugesan²

2018

Measurement and Control

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“…Karmakar et al [43] presented a dictionary-based technique to reduce shift power. Power reduction is achieved by filling the don't care bits such that transitions are minimized.…”

Section: Ordering Chains Using Both Logic Connectivity and Pattern Co...mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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“…The technique has shown a reduction in both average and peak power with minimal degradation of compression efficiency. Karmakar and Chattopadhyay [52] also proposes a dictionary-based technique; however, it only targets power reduction during shifts.…”

Section: Dictionary-based Test Data Compressionmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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Thermal-Aware Test Data Compression Using Dictionary Based Coding

Cited by 10 publications

References 12 publications

Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

Genetic Algorithm-based thermal uniformity–aware X-filling to reduce peak temperature during testing

Developments in scan shift power reduction: a survey

A survey of scan-capture power reduction techniques

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