Thermal aware energy efficient bengali unicode reader in Text analysis

Uddin, Ashraf; Rahman, Atiqur; Banshal, Sumit Kumar; Das, Teerath; Kumar, Tanesh; Pandey, Bishwajeet

doi:10.1109/icroit.2014.6798356

Cited by 14 publications

(4 citation statements)

References 7 publications

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“…Junction of working FPGA act as source and environment act as sink [1]. There is already a lot of work is going on in thermal aware design [1][2][3][4][5][6][7][8][9] . During study of existing thermal aware design methodology, we have gone through thermal aware FIR filter design [2], thermal modeling for temperature aware design [3], thermal ware ALU [4], thermal balanced design in NoC [5], thermal aware Unicode reader [6], thermal aware 3D microprocessor [7], Frame Buffer [8] and thermal aware floor planning at the micro-architectural level [9].JT is measured in terms of AT, thermal power and TJA as shown in Figure 4.…”

Section: Different Type Of Airflowmentioning

confidence: 99%

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

Kalia

Nanda

Aggarwal

et al. 2015

AMR

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

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Section: Different Type Of Airflowmentioning

confidence: 99%

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

Kalia

Nanda

Aggarwal

et al. 2015

AMR

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“…Therefore, we are going to control the parameter like room temperature, airflow, junction to ambient thermal resistance, which are responsible for increase in junction temperature of device.There is already a lot of work is going on in thermal aware design [1][2][3][4][5][6][7][8] and in Vedic multiplier [9][10][11][12][13][14][15][16][17]. During study of existing thermal aware design methodology, we have gone through thermal aware FIR filter design [1], thermal modelling for temperature aware design [2], thermal ware ALU [3], thermal balanced design in NoC [4], thermal aware Unicode reader [5], thermal aware floor planning for 3D microprocessor [6], Frame Buffer [7] and thermal aware floor planning at the micro-architectural level [8]. Novelty of this work is that we are integrating thermal aware design approach in Vedic multiplier that finally results into both energy efficient and thermal aware Vedic multiplier.LVCMOS is an acronym for low voltage complementary metal oxide semiconductor.…”

Section: Introductionmentioning

confidence: 99%

LVCMOS Based Thermal Aware Energy Efficient Vedic Multiplier Design on FPGA

Goswami

Pandey

2014

2014 International Conference on Computational Intelligence and Communication Networks

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In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind? This paper deals with that question and the whole work is going in direction to get solution of this problem with mechanism of ambient (room) temperature scaling and energy efficient LVCMOS I/O standard. LVCMOS is an acronym for low voltage complementary metal oxide semiconductor. In this Vedic multiplier, we are using three LVCMOS I/O standard. LVCMOS12 is available only in 65nm and 40nm FPGA. Rest LVCMOS18 and LVCMOS25 is available among 40nm, 65nm and 90nm FPGA. In order to test the thermal sustainability of our Vedic multiplier, we are testing it in three different room temperature 20 o C, 30 o C, and 40 o C.Using LVCMOS25, there is 12.99%, 19.23% and 10.28% reduction in power dissipation on 90nm, 65nm and 40nm respectively. For LVCMOS25, when our Vedic multiplier design is migrated from 40nm design to 90nm design, there is 87.72% reduction in power dissipation of Vedic multiplier when temperature is constant 20 o C.

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“…1, we are operating our ROM design with supported frequency of latest i7 processor in order to test the compatibility of this design with 4 th generation processor. There is already a lot of work is going on in thermal aware design [1][2][3][4][5][6][7][8]. During study of existing thermal aware design methodology, we have studied thermal aware FIR filter design [1], thermal modelling for temperature aware design [2], thermal ware ALU [3], thermal balanced design in NoC [4], thermal aware Unicode reader [5], thermal aware floor planning for 3D microprocessor [6],…”

Section: Introductionmentioning

confidence: 99%

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

Saini

Bansal

et al. 2014

AMR

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—Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient temperature is a temperature of surroundings. Airflow is measured in Linear Feet per Minute (LFM). Medium profile and high profile are two different heat sink profile available in XPower analyzer.When frequency goes from 4.0GHz to 1.0GHz, there is 21.8% reduction in clock power, 75% reduction in I/O Power, 35.6% reduction in leakage power and 53.8% reduction in total power at the same frequency.

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Thermal aware energy efficient bengali unicode reader in Text analysis

Cited by 14 publications

References 7 publications

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

LVCMOS Based Thermal Aware Energy Efficient Vedic Multiplier Design on FPGA

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

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