2016
DOI: 10.7567/jjap.55.06ja01
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The way to zeros: The future of semiconductor device and chemical mechanical polishing technologies

Abstract: For the last 60 years, the development of cutting-edge semiconductor devices has strongly emphasized scaling; the effort to scale down current CMOS devices may well achieve the target of 5 nm nodes by 2020. Planarization by chemical mechanical polishing (CMP), is one technology essential for supporting scaling. This paper summarizes the history of CMP transitions in the planarization process as well as the changing degree of planarity required, and, finally, introduces innovative technologies to meet the requi… Show more

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Cited by 32 publications
(29 citation statements)
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“…As is well known, a major requirement for the CMP process is the minimal dishing and erosion, as well as minimal levels of the surface defects [3]. Furthermore, approaching and even achieving the three-"zero" target of "0 nm planarity, 0 defects, and 0 polishing load" are the desired goals for the CMP technology [5]. Hence, it is important to evaluate the surface defect of a Cu thin film.…”
Section: Resultsmentioning
confidence: 99%
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“…As is well known, a major requirement for the CMP process is the minimal dishing and erosion, as well as minimal levels of the surface defects [3]. Furthermore, approaching and even achieving the three-"zero" target of "0 nm planarity, 0 defects, and 0 polishing load" are the desired goals for the CMP technology [5]. Hence, it is important to evaluate the surface defect of a Cu thin film.…”
Section: Resultsmentioning
confidence: 99%
“…Owing to the shrinkage of ultralarge-scale integrated circuits, new challenges for CMP have emerged recently, one of which is the small root-mean-square roughness (of the order of subnanometer) [1−4]. The initial requirement of reducing the step-height differences to about 50 nm was first changed to 30 nm, then to 10 nm, and finally to a 0 nm difference [5,6]. Furthermore, a three-"zero" target, namely, "0 nm planarity, 0 defects, and 0 polishing load", is even proposed and desired to be reached by the year 2020 [5].…”
Section: Introductionmentioning
confidence: 99%
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“…1,2 CMP of the metal components of logic devices constitute a major aspect of this technique and, like other areas of IC manufacturing, metal CMP has become quite complex while addressing the emerging demands of technology through the last decade. 3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems.…”
mentioning
confidence: 99%
“…3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems. 6 Recent studies performed in industrial facilities have also identified a critical need to further advance the fundamental understanding of metal CMP.…”
mentioning
confidence: 99%