Perspective—Electrochemical Assessment of Slurry Formulations for Chemical Mechanical Planarization of Metals: Trends, Benefits and Challenges

Abstract

With continued shrinkage of circuit dimensions, the technique of chemical mechanical planarization (CMP) has become progressively more intricate through the last decade. Since the chemical mechanism of metal CMP is governed by electrochemical effects, the complex task of CMP-slurry engineering can be economically assisted in the electroanalytical approach by using laboratory scale model systems. This article discusses how CMP has been impacted by device scaling, and examines the status of fundamental studies of metal CMP. The techniques suitable for studying model CMP systems are discussed, along with an assessment of the utilities and the practical limits of such experiments. Chemical mechanical planarization (CMP) is an essential processing step of integrated circuit (IC) fabrication. 1,2 CMP of the metal components of logic devices constitute a major aspect of this technique and, like other areas of IC manufacturing, metal CMP has become quite complex while addressing the emerging demands of technology through the last decade. 3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems. 6 Recent studies performed in industrial facilities have also identified a critical need to further advance the fundamental understanding of metal CMP. 7,8 The present article provides a perspective on these fundamental research aspects of metal CMP that are in the core of most laboratory scale studies of these systems. Device Scaling and CMP ConsiderationsThe International Technology Roadmap for Semiconductors (ITRS) specified the earlier technology nodes in terms of the DRAM half-pitch (hp), or the microprocessor's level-1 metal hp of a device. 9 Basically until the 65 nm node, the shrinkage of feature-size has continued in line with Dennard scaling, by a factor (S) of 1/ √ 2, to accommodate doubling of transistors per unit chip area (scaling as S 2 = 1/2) every two years in relation to Moore's law. 10 Increased leakage currents in the subsequent feature reductions have eventually shifted this technology trend, with the emergence of advanced multicore systems. 11 While the scaling factor of 1/ √ 2 has been largely maintained in the post-Dennard period, the newer logic devices have evolved in a more complex manner compared to their earlier counterparts. The middle-of-line (MOL) metallization scheme has emerged from the need to reduce the parasitic effects of active wiring that extends over 4 km cm −2 for >13 metal layers. 9 Novel diffusion barriers and ultra-low-k (ULK) dielectrics, Fin field effect transistors (Fin-FETs), high-k gate dielectrics, and exploratory designs/materials for local interconnects have been steadily incorporated in new device architectures in keeping with the advents of scaling sch...

Editors' Choice—In Situ Electrochemical Evaluation of Post-CMP Cleaning Reactions for Cobalt and Copper Films under Brushing Conditions

“…The PCMPC steps of chemical/electrochemical dissolution fall in the category of corrosion reactions. 4,32 Since these reactions are responsible for the E oc profiles plotted in Fig. 2, the observed OCPs can therefore be characterized as corrosion potentials (E corr ).…”

“…3 Due to this reason, (CMP and) PCMPC processes of metals can be efficiently assessed in a cost-effective approach by using electrochemical techniques. 4 Most reported electrochemical studies of PCMPC use mechanically unperturbed sample electrodes in traditional electrochemical cells, where the component of brush-cleaning remains absent. On the other hand, the chemical/electrochemical functions of PCMPC are inherently coupled to the tribological action of the brush used in this method.…”

A review on chemical and mechanical phenomena at the wafer interface during chemical mechanical planarization

“…There has been significant progress in understanding the fundamental science and technology of CMP for the past several decades. Nevertheless, most of the models, methodologies, and techniques generally use laboratory-scale model systems under the assumptions about process parameters, which may or may not be relevant to explain high-volume-production fabbased CMP processes [148]. A close collaboration between academic and industrial R&D will help us to move forward with understanding the fundamental principles and technologies of the actual CMP process by minimizing the gaps between labbased CMP models and fab-based CMP processes.…”

Study on PVA Brush Loading and Conditioning during Shallow Trench Isolation Post-CMP Cleaning Process

“…Chemical mechanical polishing (CMP) is a critical process used for global planarization of a variety of surfaces in semiconductor manufacturing, especially as technology is progressing to smaller than 10 nm nodes. [1][2][3][4] Meeting the stringent requirements for CMP and minimizing defects, especially that of particle count, has been of great interest to the overall success of the CMP process. Particles remaining on the wafer surface after CMP can embed into the surface, blocking subsequent photolithography leading to pinholes in the deposited film.…”