The ultimate RISC

Jones, Douglas R.

doi:10.1145/48675.48683

Cited by 17 publications

(19 citation statements)

References 5 publications

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“…In particular, when multiple code fragments within a single program version are made more similar, diffing tools have a harder time differentiating between them. For example, all signatures computed on opcodes occurring in a procedure would fail on a single-instruction computer [Jones 1988].…”

Section: Instruction Set Limitationmentioning

confidence: 99%

Feedback-driven binary code diversification

Coppens

Sutter

Maebe

2013

ACM Trans. Archit. Code Optim.

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As described in many blog posts and in the scientific literature, exploits for software vulnerabilities are often engineered on the basis of patches. For example, "Microsoft Patch Tuesday" is often followed by "Exploit Wednesday" during which yet unpatched systems become vulnerable to patch-based exploits. Part of the patch engineering includes the identification of the vulnerable binary code by means of reverse-engineering tools and diffing add-ons. In this article we present a feedback-driven compiler tool flow that iteratively transforms code until diffing tools become ineffective enough to close the "Exploit Wednesday" window of opportunity. We demonstrate the tool's effectiveness on a set of real-world patches and against the latest version of BinDiff.

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Section: Instruction Set Limitationmentioning

confidence: 99%

Feedback-driven binary code diversification

Coppens

Sutter

Maebe

2013

ACM Trans. Archit. Code Optim.

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“…The HA instruction set is complete and can be used to construct any Turing computable program [11]. This means that any practical program can be built using this instruction.…”

Section: Half Adder Architecturementioning

confidence: 99%

“…2). Such an approach is also known as a "transport-triggered" architecture [11]. While a MOVE architecture is really a multi-instruction architecture, it appears as a single instruction to compiler and programmer.…”

Section: Move Based Processormentioning

confidence: 99%

Single Instruction Set Architectures for Image Processing

Laplante

Gilreath²

2002

SPIE Proceedings

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For more than fifty years, computer engineers have sought to construct minimal computers using only a single instruction computer. While it might appear to be a simple academic exercise, remarkably, a rich computation paradigm can be developed using this approach, with important applications and implications in reconfigurable, chemical, optical and biological computing. More recently, the widespread use of the Field Programmable Gate Array (FPGA) has made such an approach not only desirable, but also practical.In this paper the history and motivation behind single instruction or one instruction computing (OISC) is reviewed. It is then shown how the paradigm can be used to implement a variety of imaging operations efficiently. Finally, a practical application and future work in languages and tools are presented.

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“…Our experience with some earlier research microprocessors like the U]timate/lV[ininlal RISC/CISC in [2], [3], [4] [6], DLX [1], and some o f the state-of-the-art commercial RISC/CISC processors [7], [8], [9], [10], has shown us the importance of~nifying the data and control flow executions to reduce complexity in RISC processors [5]. This simplifies even more the internal resources, the memory-cpu communication, and the control unit.…”

Section: Introductionmentioning

confidence: 99%

The RISC processor DMN-6: a unified data-control flow architecture

Paez-Monzon

Páez-Monzón²

1996

SIGARCH Comput. Archit. News

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This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concenU~tes all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control si~rnal generation for an integer functional unit. This is obtained by implementing a number of queue registers of different deepness around the datapath unit. These queues will control an assigned logic corresponding to a stage in the pipeline. The architecture reduces even more the complexity o f a pipelined program execution. The main features are : Load/Store architecture, 4-stage pipeline, integer arithmetic, sixteen byte registers, internal separate data and instruction main memories, thirteen 16-bit instruction words.

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The ultimate RISC

Cited by 17 publications

References 5 publications

Feedback-driven binary code diversification

Feedback-driven binary code diversification

Single Instruction Set Architectures for Image Processing

The RISC processor DMN-6: a unified data-control flow architecture

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