Abstract:This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concenU~tes all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control si~rnal generation for an integer functional unit. This is obtained by implementing a number of queue registers of different deepness around the datapath unit. These queues will control an assigned logic corresponding to a stage in the pipeline. The architecture red… Show more
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