The suspended-gate MOSFET (SG-MOSFET): a modeling outlook for the design of RF MEMS switches and tunable capacitors

Pott, V.; Ionescu, Adrian M.; Fritschi, R.; Hibert, C.; Flückiger, Ph.; Declercq, M.; Renaud, Philippe; Rusu, A.; Dobrescu, D.; Dobrescu, Lidia

doi:10.1109/smicnd.2001.967431

Cited by 7 publications

(5 citation statements)

References 2 publications

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“…Precise modelling of NEMS devices is particularly complicated because of the interaction between electrical and mechanical components. However, using duality between electrical and mechanical systems, an entirely electrical SPICE model has been proposed in [34] for NEMS devices. These two kinds of systems are dual because of the similarity of the differential equations that govern electrical and mechanical systems as shown in Fig.…”

Section: Modelling Of Sg-fet Devicesmentioning

confidence: 99%

“…Additionally, different forces ( f ), which pull the suspended gate towards the substrate, are modelled with a voltage-controlled voltage source ( f (V g )). Since f (V g ) is a complicated function of several parameters, a polynomial approximation is used through curve fitting [34].…”

Section: Modelling Of Sg-fet Devicesmentioning

confidence: 99%

“…The next step, as shown in Fig. 16b, is self-aligned definition of ) is obtained during model calibration with a similar approach as in [34]; L and R values are calculated based on formulas presented in [35]. source and drain area for CMOS devices.…”

Section: Fabrication Feasibility Of Hybrid Nems-cmos Circuitsmentioning

confidence: 99%

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Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs

Dadgour

Banerjee

2009

IET Comput. Digit. Tech.

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Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution to tackle the leakage issue, which is proposed in this work, is to integrate nano-electro-mechanical switches (NEMS) with CMOS technology. Hybrid NEMS-CMOS technology takes advantage of both near-zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low-power dynamic OR gates, static random access memory (SRAM) cells and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80% lower switching power and almost zero-leakage power consumption with minor delay penalty. However, the hybrid OR gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that a hybrid NEMS-CMOS SRAM cell can achieve almost 8Â lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in up to three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches. The characteristics of an ideal switch can be described as one having abrupt transition between ON and OFF states with high ON current and zero OFF current. However, all

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Section: Modelling Of Sg-fet Devicesmentioning

confidence: 99%

Section: Modelling Of Sg-fet Devicesmentioning

confidence: 99%

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Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs

Dadgour

Banerjee

2009

IET Comput. Digit. Tech.

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“…Precise modeling of NEMS devices is particularly complicated due to the interaction between electrical and mechanical components. However, using the electrical equivalents of mechanical variables, an entirely electrical SPICE model has been proposed in [23] for NEMS devices. In this model, each mechanical variable (shown in Figure 6 (a)) is replaced with its electrical equivalent, which leads to the SPICE model presented in Figure 6 (b).…”

Section: Modeling Of Nems Devicesmentioning

confidence: 99%

“…Additionally, different forces (F), which pull the suspended gate toward the substrate, are modeled with a voltage-controlled source (f(Vg)). Since f(Vg) is a complicated analytical function, a polynomial approximation is used through curve fitting [23]. According to this model, ON current of the NEMS device is lower than that of an identically-sized CMOS device because actual gate voltage for the NEMS transistor is smaller than Vg due to the voltage drop caused by f(Vg) (Figure 6 (b)).…”

Section: Modeling Of Nems Devicesmentioning

confidence: 99%

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Dadgour

Banerjee

2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, codesign of hybrid NEMS-CMOS as low power dynamic OR gates, SRAM cells, and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80% lower switching power and almost zero leakage power consumption with minor delay penalty. However, the hybrid gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that the proposed hybrid SRAM cell can achieve almost 8X lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in upto three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.

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Simple and fast simulation approach to investigate the NBTI effect on suspended gate MOS devices

Tahanout

Tahi

Nadji

et al. 2019

International Journal of Electronics Letters

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The suspended-gate MOSFET (SG-MOSFET): a modeling outlook for the design of RF MEMS switches and tunable capacitors

Cited by 7 publications

References 2 publications

Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs

Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Simple and fast simulation approach to investigate the NBTI effect on suspended gate MOS devices

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