2007
DOI: 10.1145/1278480.1278559
|View full text |Cite
|
Sign up to set email alerts
|

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Abstract: Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, codesign of hybrid NEMS-CMOS as low power dynamic OR gates, SRAM cells, and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-8… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1

Citation Types

0
12
0
2

Year Published

2009
2009
2018
2018

Publication Types

Select...
5
2
1

Relationship

0
8

Authors

Journals

citations
Cited by 37 publications
(16 citation statements)
references
References 30 publications
0
12
0
2
Order By: Relevance
“…Prestasi cemerlang yang dicapai oleh sebilangan kecil suis NEM telah mendapat tempat dalam pelan halatuju ITRS sebagai pengganti berpotensi atau hibrid yang melengkapkan peranti CMOS konvensional kerana beberapa kelebihan seperti penggunaan komponen yang lebih kecil dalam peranti seterusnya mengurangkan pensuisan dinamik sebanyak 60% telah dilaporkan untuk hibrid get OR (Dadgour & Banerjee 2007). Selain itu, hanya dua suis NEM digunakan untuk membuat get empat-terminal XOR, sedangkan get logik ini memerlukan sekurangkurangnya sepuluh transistor CMOS untuk membuatnya.…”
Section: Kesimpulan Dan Pandanganunclassified
See 1 more Smart Citation
“…Prestasi cemerlang yang dicapai oleh sebilangan kecil suis NEM telah mendapat tempat dalam pelan halatuju ITRS sebagai pengganti berpotensi atau hibrid yang melengkapkan peranti CMOS konvensional kerana beberapa kelebihan seperti penggunaan komponen yang lebih kecil dalam peranti seterusnya mengurangkan pensuisan dinamik sebanyak 60% telah dilaporkan untuk hibrid get OR (Dadgour & Banerjee 2007). Selain itu, hanya dua suis NEM digunakan untuk membuat get empat-terminal XOR, sedangkan get logik ini memerlukan sekurangkurangnya sepuluh transistor CMOS untuk membuatnya.…”
Section: Kesimpulan Dan Pandanganunclassified
“…Oleh kerana saiz peranti semikonduktor dikurangkan kepada beberapa puluhan nanometer dan permintaan untuk lebih banyak aplikasi terus meningkat, strategi lain amat diperlukan. Sebagai contoh, suis NEM adalah salah satu calon untuk menyelesaikan isu penggunaan kuasa yang tinggi dalam peranti complementary metal-oxide semiconductor (CMOS) sekiranya saiz peranti dikurangkan kepada saiz nano (Dadgour & Banerjee 2007;Peschot et al 2015).…”
unclassified
“…The subthreshold leakage is mainly affected by the subthreshold swing (S) of a device, which is defined as the amount of gate voltage reduction to reduce the subthreshold current by one decade (S = dVgs/dlogId) [3]. For bulk CMOS, the subthreshold swing has a substantially lower limit of 60 mV/decade, which leads to a large increase in the power density [4]. This limitation prevents manufacturers from fabricating smaller devices and forces them to look for alternative solutions targeting higher performance and efficiency.…”
Section: Introductionmentioning
confidence: 99%
“…In spite of the large mechanical delay and limited number of reliable cycles, NEMs have been useful for a wide range of applications such as FPGAs (used as programmable routing switches) [8], adders [9], flip-flops [10], memories [4,11], DACs [9], and ADCs [9], where the long switching time and limited number of hits are not important issues. Most of the mentioned circuits use the benefits of combining NEMs and CMOS technology in order to highlight the advantage points of each technology and alleviate the disadvantages to achieve low-power and high-performance operation for some critical components.…”
Section: Introductionmentioning
confidence: 99%
“…Various enhancements for MTCMOS technologies have been proposed to suppress the sleep transistor leakage current [6]. Moreover it has been suggested that nano-electromechanical FETs (NEM-FETs) are viable candidates to replace the High-V t FET based sleep transistor [7], [8]. However, although fabrication feasibility of simple hybrid CMOS-NEMS circuits has been reported in [9], further technological enhancements are needed for such an approach to become a potentially viable industrial solution.…”
Section: Introductionmentioning
confidence: 99%