Hybrid NEMS–CMOS integrated circuits: a novel strategy for energy-efficient designs

Abstract

Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution to tackle the leakage issue, which is proposed in this work, is to integrate nano-electro-mechanical switches (NEMS) with CMOS technology. Hybrid NEMS-CMOS technology takes advantage of both near-zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low-power dynamic OR gates, static random access memory (SRAM) cells and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80% lower switching power and almost zero-leakage power consumption with minor delay penalty. However, the hybrid OR gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that a hybrid NEMS-CMOS SRAM cell can achieve almost 8Â lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in up to three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches. The characteristics of an ideal switch can be described as one having abrupt transition between ON and OFF states with high ON current and zero OFF current. However, all

Improved reconfigurability and noise margins in threshold logic gates via back-gate biasing in DG-MOSFETs

“…For the power dissipation, it is important to emphasize that DG-MOSFETs, like other multi-gate MOSFETs, are realistic candidates only for sub-22 nm technology nodes, where the V DD B 0.8 V and the transistor on-current is already saturated due to transistor scaling limitations such as series parasitics, velocity saturation, etc. The biggest power concern in these nano-scale transistors switching at several GHz frequency is not the on-current pathways but the static and dynamic off-current paths due to interconnects, gate and junction leakage [14,15]. In such drastically scaled systems, transistor count becomes a primary concern in minimizing the power leakage, a point also implied by the simulation data in Table 1.…”

Peranti Suis Sistem Nanoelektromekanikal (NEMS) Berunsurkan Grafin dan Tiub Nano Karbon (CNT)

“…Dalam pada itu, kebocoran sub-ambang iaitu kebocoran arus elektrik dalam keadaan mod-tertutup akan meningkat dengan ketara bagi peranti transistor CMOS konvensional apabila saiz perantinya dikecilkan (Dadgour & Banerjee 2009). Berbeza dengan situasi suis 2-T NEM, apabila kebocoran sub-ambang pada peranti dalam keadaan suis terbuka dapat dikurangkan melalui terowong vakum dan arus anjakan gerakan Brownian melalui ruang fizikal antara terminal punca dan saliran.…”

Nanoelectromechanical Switches for Low-Power Digital Computing

“…Simulation-based studies project NEM relay technology to be able to achieve more than a one order of magnitude improvement in energy efficiency as compared with CMOS technology, for an equivalent area and a mechanical switching delay of 10 ns [17,50]. Hybrid CMOS/NEM technology can potentially achieve the advantages of high-speed CMOS operation together with low-power NEM relay operation [67]. For example, a hybrid NEMS/CMOS static random-access memory (SRAM) cell design for lower static power dissipation and improved cell stability is proposed in [48], and projected to provide a reduction in energy loss of 85%, improvement in write and read times by 60% and 10%, respectively, and an improved static noise margin.…”