The statistics of NBTI-induced V/sub T/ and β mismatch shifts in pMOSFETs

Rauch, S.E.

doi:10.1109/tdmr.2002.805119

Cited by 82 publications

(30 citation statements)

References 7 publications

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“…www.intechopen.com A few works have been published in the literature to estimate the statistical variations in temporal NBTI degradation (Rauch, 2002;2007;Rosa et al, 2006;Kang et al, 2007). Their assumption is the number of broken bonds in the channel is a Poisson random variable, and correspondingly V th follows the Poisson distribution.…”

Section: Introductionmentioning

confidence: 99%

Statistical prediction of circuit aging under process variations

Wang

Reddy

Yang

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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Section: Introductionmentioning

confidence: 99%

Statistical prediction of circuit aging under process variations

Wang

Reddy

Yang

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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“…Using the models, we carried out HSPICE Monte Carlo simulations on 10000 samples. For NBTI degradation in PMOS transistors, we implemented the reaction-diffusion (RD) model [42] and assumed Poisson's distribution on the interface trap numbers among different microscopic samples [43]. The average number of interface traps was calibrated against [44].…”

Section: Resultsmentioning

confidence: 99%

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Hassan

Roy

2017

Microelectronics Reliability

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Abstract-Bias Temperature Instability (BTI) is a majorreliability concern in CMOS technology, especially with High dielectric constant (High-κ/HK) metal gate (MG) transistors. In addition, the time independent process induced variation has also increased because of the aggressive scaling down of devices. As a result, the faster devices at the lower threshold voltage distribution tail experience higher stress, leading to additional skewness in the BTI degradation. Since time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) in NMOS devices are correlated to BTI, it is necessary to investigate the effect of time zero variability on all these effects simultaneously.To that effect, we propose a simulation framework to model and analyze the impact of time-zero variability (in particular, random dopant fluctuations) on different aging effects. For small area devices (~1000 nm 2 ) in 30nm technology, we observe significant effect of Random Dopant Fluctuation (RDF) on BTI induced variability (σ ΔVth ). In addition, the circuit analysis reveals similar trend on the performance degradation. However, both TDDB and SILC show weak dependence on RDF. We conclude that the effect of RDF on V th degradation cannot be disregarded in scaled technology and needs to be considered for variation tolerant circuit design.

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“…The intrinsic variations of NBTI are studied in (Rauch, 2002). The expression of variation in △V th shift is…”

Section: Nbtimentioning

confidence: 99%