Statistical prediction of circuit aging under process variations

Wang, Wenping; Reddy, V.; Yang, Bo; Balakrishnan, Varsha; Krishnan, S.; Cao, Yu

doi:10.1109/cicc.2008.4672007

Cited by 64 publications

(22 citation statements)

References 30 publications

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“…The pessimistic delay for each circuit is obtained by assuming the worst-case workload at every gate input, as in [9]- [11]. Such pessimistic delays, typically used to define a presilicon aging margin, may result in high power/area overheads during optimization [1], [5].…”

Section: Introductionmentioning

confidence: 99%

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

Sengupta¹,

Sapatnekar²

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Bias temperature instability (BTI) induced delay shifts in a circuit depend strongly on its operating environment. While sensors can capture some operating parameters, they are ineffective in measuring vital performance shifts due to changes in the workloads and signal probabilities. This paper determines the delay of an aged circuit by amalgamating more frequent measurements on ringoscillator sensors with infrequent online delay measurements on a monitored circuit to recalibrate the sensors. Our approach reduces the pessimism in predicting circuit delays, thus permitting lower delay guardbanding overheads compared to conventional methods.

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Section: Introductionmentioning

confidence: 99%

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

Sengupta¹,

Sapatnekar²

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…The specific degraded delay depends on input vectors during operation, which are not known ahead of time. A worst-case scenario is considered to guarantee reliable operation [21], [22], [38]. As seen in (17), delay decreases at lower temperatures.…”

Section: H Delaymentioning

confidence: 99%

“…Therefore, a safe and tight upper bound for circuit delay degradation under worst-case signal probabilities is required for reliable operation. In most practical cases, it can be obtained by assuming WC-K aging of 0.95 for the entire circuit [5], [21], [22], [38]. Worst-case aging during time-step i implies that the system is always in the active mode under worst-case workload, i.e., η (i) = 1 and K aging(i) = WC-K aging .…”

Section: E Threshold Voltagementioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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“…They differ in the type of reliability effects considered and the type of circuits studied. For digital circuits, NBTI-aware statistical timing analysis considering process variations are proposed in (Vaidyanathan, Oates, Xie & Wang, 2009), ), (Wang et al, 2008) and (Lu et al, 2009). Authors in (Vaidyanathan, Oates, Xie & Wang, 2009) build up gate-level delay fall-out model by propagating the device parameter fall-out model due to NBTI and process variations into the gate delay model.…”

Section: State Of the Artmentioning

confidence: 99%

“…They consider in addition the intrinsic variations of NBTI process in ). Using variation-aware gate delay model, the timing behavior of a path is modeled in (Wang et al, 2008). Authors in (Lu et al, 2009) apply the NBTI aging-aware statistical timing analysis into circuit level.…”

Section: State Of the Artmentioning

confidence: 99%

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

Pan¹,

Graeb²

2011

Advances in Analog Circuits

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Statistical prediction of circuit aging under process variations

Cited by 64 publications

References 30 publications

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

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