The StageNet fabric for constructing resilient multicore systems

Abstract

Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leading to increasing operating temperatures and current densities. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Consequently, high reliability and fault tolerance, which have traditionally been subjects of interest for high-end server markets, are now getting emphasis in the mainstream desktop and embedded systems space. The popular solution for this has been the use of redundancy at a coarse granularity, such as dual/triple modular redundancy. In this work, we challenge the practice of coarse-granularity redundancy by identifying its inability to scale to high failure rate scenarios and investigating the advantages of finer-grained configurations. To this end, this paper presents and evaluates a highly reconfigurable multicore architecture, named StageNet (SN), that is designed with reliability as its first class design criteria. SN relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of a chip, gracefully degrading performance towards the end of life. Our results show that the proposed SN architecture can perform nearly 50% more cumulative work compared to a traditional multicore.

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

“…Gupta et al [5] have developed StageNet (SN) that is a flexibility-oriented architecture and the pipeline stages are connected by cross-bar-switch based interconnection network. The cross-bar switches are the main components in the SN that provides distinct feature for stage-level reconfiguration.…”

“…StageNet (SN) architecture [5] has been positioned as a good candidate for system recovery as it scales well with the increase in area available for redundancy. Logically, stages are a convenient boundary because pipeline architectures divide work at the level of stages (e.g., fetch, decode, etc.).…”

“…With the increasing defect rate in semiconductor technology, it will not be uncommon to see a rapid degradation in throughput for these systems as single device failures cause entire cores to be decommissioned, often times with the majority of the core still intact and functional [3,4]. In contrast, the works in [5,6] argue the case for reconfiguration and redundancy at a finer granularity. These works present stage-level reconfigurable CMP architecture designed as a network of pipeline stages, rather than isolated cores in a CMP.…”

“…However, such a reconfigurable CMP architecture suffers from its significant area and power consumption by heavy interconnections among the pipeline stages with many cores [5]. On the other hand, the architecture [6] having less interconnections shows less flexibility and weaker fault-tolerant capability than the former case [5].…”

“…On the other hand, the architecture [6] having less interconnections shows less flexibility and weaker fault-tolerant capability than the former case [5]. Therefore, efficient interconnection structure is necessary to provide cost-effective stage-level reconfigurable CMP with great flexibility.…”