Fault Tolerant Computer Architecture

Sorin, Daniel J.

doi:10.1007/978-3-031-01723-0

Cited by 46 publications

(3 citation statements)

References 169 publications

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“…This reduction of resources, especially regarding FFs, represents a good result regarding reliability facing Single Event Upsets (SEUs) since FFs are one of the most sensitive parts of circuits in the space environment. Moreover, unlike Single Event Transients (SETs), in FFs, the bit-flips remain stored and potentially create problems up to the FF update [17].…”

Section: B Hdl Resultsmentioning

confidence: 99%

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression

Grignani,

Santos,

Dilillo

et al. 2023

2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Several remote sensing applications that collect specific data in the space environment use images capable of providing a large volume of information, known as hyperspectral images. Given the amount of data, one of the most critical issues in applications that use hyperspectral images is the demanded for compression, which also affects restrictions on the storage capacity and processing in space applications. This work aimed to implement hyperspectral image compressors, considering the standard by the CCSDS (Consultative Committee for Space Data Systems). The solutions were implemented using a High-Level Synthesis tool (HLS) and a manual description in a Hardware Description Language (HDL). Results show that, compared to the software solution, the HLS and the HDL implementation accelerated the application by 1.6× and 4×, respectively. For images up to 512 spectral bands, the HLS solution presented a throughput of 9.11 MSa/s, while the HDL solution can process 21.47 MSa/s, which meets the real-time requirements of the standard. The HDL solution uses about 3× fewer LUTs (Look-Up Tables) LUTs and 8× fewer FFs (Flip-Flops) than the HLS implementation. Due to the low cost observed in the results, we intend to harden the accelerator and integrate it into a future multi-core satellite system.

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Section: B Hdl Resultsmentioning

confidence: 99%

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression

Grignani,

Santos,

Dilillo

et al. 2023

2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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“…For cluster computing cyber-physical systems, especially in real-time, the key is to ensure reliability and fault tolerance while maintaining the continuity of the computing process. The achievement of high and stable performance indicators, reliability, fault tolerance [1][2][3], and security of computer systems is facilitated by the use of technologies for consolidation of clustering and virtualization resources, accompanied by replication and migration of virtual machines between physical servers. Migration and replication of virtual machines speed up the reconfiguration process after failures of physical resources and contribute to support the continuity of the computing process required for managing cyber-physical systems and real-time technological processes [4][5][6].…”

mentioning

confidence: 99%

Evaluation of a Cyber-Physical Computing System with Migration of Virtual Machines during Continuous Computing

Bogatyrev

Derkach

2020

Computers

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The Markov model of reliability of a failover cluster performing calculations in a cyber-physical system is considered. The continuity of the cluster computing process in the event of a failure of the physical resources of the servers is provided on the basis of virtualization technology and is associated with the migration of virtual machines. The difference in the proposed model is that it considers the restrictions on the allowable time of interruption of the computational process during cluster recovery. This limitation is due to the fact that, if two physical servers fail, then object management is lost, which is unacceptable. Failure occurs if their recovery time is longer than the maximum allowable time of interruption of the computing process. The modes of operation of the cluster with and without system recovery in the event of a failure of part of the system resources that do not lead to loss of continuity of the computing process are considered. The results of the article are aimed at the possibility of assessing the probability of cluster operability while supporting the continuity of computations and its running to failure, leading to the interruption of the computational (control) process beyond the maximum permissible time. As a result of the calculation example for the presented models, it was shown that the mean time to failure during recovery under conditions of supporting the continuity of the computing process increases by more than two orders of magnitude.

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“…In this paper we Error detection is the most important aspect of fault tolerance because a processor has to be aware of a problem before it can tolerate it. Error De-tection Code (EDC) has been incorporated into most commercial computers [41,42]. Moreover, the most of the processors incorporate Error Correction Code (ECC) in every level of cache hierarchy (e.g.…”

Section: Error Detection and Error Correction Codesmentioning

confidence: 99%

Cache memory design in the FinFET era

Jakšić¹

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The major problem in the future technology scaling is the variations in process parameters that are interpreted as imperfections in the development process. Moreover, devices are more sensitive to the environmental changes of temperature and supply volt- age as well as to ageing. All these influences are manifested in the integrated circuits as increased power consumption, reduced maximal operating frequency and increased number of failures. These effects have been partially overcome with the introduction of the FinFET technology which have solved the problem of variability caused by Random Dopant Fluctuations. However, in the next ten years channel length is projected to shrink to 10nm where the variability source generated by Line Edge Roughness will dominate, and its effects on the threshold voltage variations will become critical. The embedded memories with their cells as the basic building unit are the most prone to these effects due to their the smallest dimensions. Because of that, memories should be designed with particular care in order to make possible further technology scaling. This thesis explores upcoming 10nm FinFETs and the existing issues in the cache memory design with this technology. More- over, it tries to present some original and novel techniques on the different level of design abstraction for mitigating the effects of process and environmental variability. At first original method for simulating variability of Tri-Gate Fin- FETs is presented using conventional HSPICE simulation environment and BSIM-CMG model cards. When that is accomplished, thorough characterisation of traditional SRAM cell circuits (6T and 8T) is performed. Possibility of using Independent Gate FinFETs for increasing cell stability has been explored, also. Gain Cells appeared in the recent past as an attractive alternative for in the cache memory design. This thesis partially explores this idea by presenting and performing detailed circuit analysis of the dynamic 3T gain cell for 10nm FinFETs. At the top of this work, thesis shows one micro-architecture optimisation of high-speed cache when it is implemented by 3T gain cells. We show how the cache coherency states can be used in order to reduce refresh energy of the memory as well as reduce memory ageing. El principal problema de l'escalat la tecnologia són les variacions en els paràmetres de disseny (imperfeccions) durant procés de fabricació. D'altra banda, els dispositius també són més sensibles als canvis ambientals de temperatura, la tensió d'alimentació, així com l'envelliment. Totes aquestes influències es manifesten en els circuits integrats com l'augment de consum d'energia, la reducció de la freqüència d'operació màxima i l'augment del nombre de xips descartats. Aquests efectes s'han superat parcialment amb la introducció de la tecnologia FinFET que ha resolt el problema de la variabilitat causada per les fluctuacions de dopants aleatòries. No obstant això, en els propers deu anys, l'ample del canal es preveu que es reduirà a 10nm, on la font de la variabilitat generada per les rugositats de les línies de material dominarà, i els seu efecte en les variacions de voltatge llindar augmentarà. Les memòries encastades amb les seves cel·les com la unitat bàsica de construcció són les més propenses a sofrir aquests efectes a causa de les seves dimensions més petites. A causa d'això, cal dissenyar les memòries amb una especial cura per tal de fer possible l'escalat de la tecnologia. Aquesta tesi explora la tecnologia de FinFETs de 10nm i els problemes existents en el disseny de memòries amb aquesta tecnologia. A més a més, presentem noves tècniques originals sobre diferents nivells d'abstracció del disseny per a la mitigació dels efectes les variacions tan de procés com ambientals. En primer lloc, presentem un mètode original per a la simulació de la variabilitat de Tri-Gate FinFETs usant entorn de simulació HSPICE convencional i models de tecnologia BSIMCMG. Després, es realitza la caracterització completa dels circuits de cel·les SRAM tradicionals (6T i 8T) conjuntament amb l'ús de Gate-independent FinFETs per augmentar l'estabilitat de la cèl·lula.

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Fault Tolerant Computer Architecture

Cited by 46 publications

References 169 publications

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression

A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression

Evaluation of a Cyber-Physical Computing System with Migration of Virtual Machines during Continuous Computing

Cache memory design in the FinFET era

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