The Shuffle-Exchange Mesh Topology for 3D NoCs

Sharifi, Akbar; Sabbaghi‐Nadooshan, Reza; Sarbazi-Azad, Hamid

doi:10.1109/i-span.2008.23

Cited by 8 publications

(9 citation statements)

References 12 publications

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“…Finally, the average degree of multiplexing of a virtual channel in the network can be calculated by averaging over all dimensions and expressed as: The horizontal axis in the figures shows the traffic generation rate (and with increasing this we have low, medium, and heavy traffics) and the vertical axis shows the mean message latency [49][50][51]. As can be seen in the figures, the proposed model accurately matches under both low and moderate traffic loads.…”

Section: The Proposed Performance Modelmentioning

confidence: 60%

Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips

Sabbaghi‐Nadooshan

Patooghy

2015

Microprocessors and Microsystems

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Section: The Proposed Performance Modelmentioning

confidence: 60%

Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips

Sabbaghi‐Nadooshan

Patooghy

2015

Microprocessors and Microsystems

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“…Compared with a traditional mesh, it can reduce the diameter with the same cost by replacing some links with nonadjacent connections based on the shuffle and exchange operations. The optimal 3D layout scheme of 2D SEM that can reduce nearly 30 percent of the link power has also been proposed [24].…”

Section: Related Workmentioning

confidence: 99%

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Matsutani

Koibuchi

Yamada

et al. 2009

IEEE Trans. Parallel Distrib. Syst.

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The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for lowlatency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.

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“…Currently, massive data exchange is very common within the information systems at different scales. On a multi-processor system, different processors work together through a switching network to provide high-power data processing capability [1]- [3]. This is also true for mega data centers, where more than 10 5 servers [4] are interconnected via a large-scale switching network to deliver high-quality cloud computing service or high-performance computation service.…”

Section: Introductionmentioning

confidence: 99%

“…Second, the structure of SENs is very regular and thus easy to deploy [4], [13]. Third, the SEN has a less network diameter than other networks, and thus less implementation cost [3]. Fourth, the routing algorithm of the SEN is simple since it has a self-routing property [14], [15]: the path between an input-output pair is uniquely determined by the addresses of the input and the output.…”

Section: Introductionmentioning

confidence: 99%

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AWG-based Nonblocking Shuffle-Exchange Networks

Ding

Lee

et al. 2019

Preprint

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Optical shuffle-exchange networks (SENs) have wide application in different kinds of interconnection networks. This paper proposes an approach to construct modular optical SENs, using a set of arrayed waveguide gratings (AWGs) and tunable wavelength converters (TWCs). According to the wavelength routing property of AWGs, we demonstrate for the first time that an AWG is functionally equivalent to a classical shuffle network by nature. Based on this result, we devise a systematic method to design a large-scale wavelength-division-multiplexing (WDM) shuffle network using a set of small-size AWGs associated with the same wavelength set. Combining the AWG-based WDM shuffle networks and the TWCs with small conversion range, we finally obtain an AWG-based WDM SEN, which not only is scalable in several ways, but also can achieve 100% utilization when the input wavelength channels are all busy. We also study the routing and wavelength assignment (RWA) problem of the AWG-based WDM SEN, and prove that the self-routing property and the nonblocking routing conditions of classical SENs are preserved in such AWG-based WDM SEN.

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The Shuffle-Exchange Mesh Topology for 3D NoCs

Cited by 8 publications

References 12 publications

Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips

Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

AWG-based Nonblocking Shuffle-Exchange Networks

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