Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Abstract

The topological explorations of on-chip networks are important for efficiently using their enormous wire resources for lowlatency and high-throughput communications using a modest silicon budget. In this paper, we propose a novel tree-based interconnection network called Fat H-Tree that meets these requirements. A Fat H-Tree provides a torus structure by combining two folded H-Tree networks and is an attractive alternative to tree-based networks such as the Fat Trees in a microarchitecture domain. We introduce its chip layout schemes based on a folding technique for 2D and 3D ICs. Three deadlock-free routing schemes are proposed for Fat H-Tree. We evaluate the performance of Fat H-Tree and other tree-based networks using real application traces. In addition, the network logic area, wire resource, and energy consumption of Fat H-Tree are compared with other topologies, based on a typical implementation of on-chip routers synthesized with a 90-nm standard cell library. The results show that 1) a Fat H-Tree outperforms a Fat Tree with two upward and four downward connections in terms of the throughput and average hop count, 2) a Fat H-Tree requires 19.8 percent-27.8 percent smaller network logic area than the Fat Tree, 3) a Fat H-Tree consumes slightly less energy than the Fat Tree does, and 4) a Fat H-Tree uses slightly more wire resources than the Fat Tree, but the current process technology can provide sufficient wire resources for implementing Fat-H-Tree-based on-chip networks.

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

“…After exploring the network in twodimensional planar layout, they added bypass channels, so that the power loss and latency can be reduced. Hsu et al proposed a fat H-Tree NoC [33]. They placed several fat-tree networks on the same planar space, and made shortcuts among those networks.…”

An analytical model for on-chip interconnects in multimedia embedded systems

“…The studies on performance evaluation of on-chip interconnects have been widely reported in the literature [Ascia et al 2008;Kodi, Sarathy and Louri 2008;Matsutani et al 2009;Pande et al 2005;Sanchez, Michelogiannakis and Kozyrakis 2010]. However, most of these studies are based on the use of simulation experiments to evaluate the performance of interconnects in NoC architecture.…”

“…To minimise the performance degradation caused by the reduced buffer size, the circuit level enhancements were deployed to the existing repeaters to double the buffers when required. Matsutani et al [Matsutani et al 2009] proposed a tree-based interconnection network so as to efficiently use enormous wire resources for low-latency and high-throughput communication in NoC and employed the simulation study to evaluate the performance of interconnection networks. Pande et al [Pande et al 2005] developed a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of on-chip interconnection architectures and explored the design trade-offs that characterise the NoC for the optimal development of integrated network-based design.…”

Exploring partitioning methods for multicast in 3D bufferless Network on Chip

“…The 3D integrated circuit is also an attractive way for Network on chip. The 3D NoC architecture is widely studied in the network topology [7], router architecture [8], and routing algorithms [9].…”