Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

Abstract

Abstract-Chip multiprocessor (CMP) is becoming increasingly popular in the processor industry. Efficient network-on-chip (NoC) that has similar performance to the processor cores is important in CMP design. Fat-tree based on-chip network has many advantages over traditional mesh or torus based networks in terms of throughput, power efficiency and latency. It has a bright future in the development of CMP. However, the floorplan design of the fat-tree based NoC is very challenging because of the complexity of topology. There are a large number of crossings and long interconnects, which cause severe performance degradation in the network. In electronic NoCs, the parasitic capacitance and inductance will be significant. In optical ones, large crosstalk noise and power loss will be introduced. The novel contribution of this paper is to propose a method to optimize the fat-tree floorplan, which can effectively reduce the number of crossings and minimize the interconnect length. Two types of floorplans are proposed, which could be applied to fat-tree based networks of arbitrary size. Compared with the traditional one, our floorplans could reduce more than 87% of the crossings. Since the traversal distance for signals is related to the aspect ratio of the processor cores, we also present a method to calculate the optimum aspect ratio of the processor cores to minimize the traversal distance.

Layout optimization methodology for ring-based on-chip optical network

“…The non-optimized and optimized ring-based networks, a typical kind of switch-based network called λrouter and a fat-tree network with an optimized layout [30] will be compared with respect to the total number of cross points. The network size will be set to support 4, 6, and 8 cores' unicast, multicast and broadcast communication without any intention between cores.…”

Fat‐tree‐based optical networks‐on‐chip with WDM: crosstalk noise exploiting

“…where L p l c is the propagation loss of link c. P in λ n L c λ n indicates the final output power of optical signal λ n passing through link c, N i, j|1 c and N i, j|2 c denote crosstalk noise produced by optical routers located in the latter half and the first half of link c under worst-case configurations and are expressed as (28). In (27) (see (28))…”

Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

“…The nanophotonic architecture can be optimized in order to minimize the laser power consumption. In previous studies, a novel fat-tree floorplan [6] and a ring-based packet-switched optical network-on-chip (RPNoC) [7] were proposed to reduce the number of hops of routing path so as to yield lower energy consumption. Recently, an optimized routing algorithm based on Gaussian-based ONoCs was proposed to improve the optical signal-to-noise ratio (OSNR) [8].…”