The Role of the Fermi Level Pinning in Gate Tunable Graphene-Semiconductor Junctions

Abstract

Graphene based transistors relying on a conventional structure cannot switch properly because of the absence of an energy gap in graphene. To overcome this limitation, a barristor device was proposed, whose operation is based on the modulation of the graphene-semiconductor (GS) Schottky barrier by means of a top gate, and demonstrating an ON-OFF current ratio up to 10 5 . Such a large number is likely due to the realization of an ultra clean interface with virtually no interface trapped charge. However, it is indeed technologically relevant to know the impact that the interface trapped charges might have on the barristor's electrical properties. We have developed a physics based model of the gate tunable GS heterostructure where non-idealities such as Fermi Level Pinning (FLP) and a "bias dependent barrier lowering effect" has been considered. Using the model we have made a comprehensive study of the barristor's expected digital performance.

Analog Circuit Applications Based on All‐2D Ambipolar ReSe2 Field‐Effect Transistors

“…The transfer characteristics ( I ds – V bg ) for different V ds at room temperature are shown in Figure e and showed clear ambipolar behavior. Owing to the relatively small bandgap of ReSe 2 compared with that of MoS 2 (1.2–1.96 eV) and the Fermi level in graphene, which is tunable with bias, the majority conduction carrier could be either electrons or holes . The source/drain series resistance R sd values were 8.7 × 10 5 and 2.1 × 10 5 Ω µm −1 for the p‐ and n‐channel regime, respectively, extracted based on the Y ‐function method .…”

Photoresponse of Graphene-Gated Graphene-GaSe Heterojunction Devices

“…In doing so, we have used the device model fully explained in previous works. 24 , 35 In this model, the device operation can be understood by analyzing the electrical behavior of its equivalent circuit, which made of two back-to-back gate tunable diodes, referred to as D 1 and D 2 , as shown in the inset of Figure 2 a. The current controlled by each of the gate tunable diodes have been computed with eq 1 .…”

“…V refers to the applied bias. For the simulations we have used A = 12 μm 2 , A * = 4.5 × 10 –6 A μm –2 K –2 , and T = 300 K. The SBH has been computed by self-consistently solving the transport eq 1 together with the electrostatic equations governing the metal-oxide-graphene-semiconductor (MOGS) heterostructure, as detailed in refs ( 24 ) and ( 35 ). For the reader convenience the procedure has been schematized in Figure S2 , where the band diagram of the MOGS heterostructure, corresponding to a vertical cut across the diode, can be also found.…”

Contact resistance extraction of graphene FET technologies based on individual device characterization

“…The extraction methods have also been applied to data from a physics-based model (Landauer transport theory) [45] of a graphene-based transistor-like device (see Fig. 10 in [45]) with a reference contact resistance in the model L g (nm)…”

“…-0.7 -0.6 -0.5 -0.4 -0.3 4)). [45] embraces a resistance associated to a potential barrier R C,PB,ref of 250 kΩ and a resistance associated to other interfacial layers R C,IL (value not reported). Notice that a metal/oxide/graphene/semiconductor stack is considered within the contact region and that the oxide is isotropic and isometric along the whole device in the direction of the carrier transport including the gated-graphene region under the top-gate [45].…”