The Robustness of Modern Deep Learning Architectures against Single Event Upset Errors

Arechiga, Austin P.; Michaels, Alan J.

doi:10.1109/hpec.2018.8547532

Cited by 27 publications

(20 citation statements)

References 23 publications

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“…When the application domain is a safety-critical system-for example, in automotive, avionics or space industries-reliability becomes an important requirement [22,23]. Reliability evaluation and fault-tolerant design for FPGA-based CNNs have recently received a great deal of interest from researchers [24][25][26]. The proposed VR-ZyCAP can enable soft error injection in user memories as well as configuration memory [26].…”

Section: Design Of Fault Tolerant Fpga-based Cnnsmentioning

confidence: 99%

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

et al. 2021

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Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

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Section: Design Of Fault Tolerant Fpga-based Cnnsmentioning

confidence: 99%

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

et al. 2021

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“…One modern and compact network, SqueezeNet [10], has been selected as our primary test case, as it is representative of the networks used in embedded applications. Since many, previous fault tolerance studies [7], [9], [11] have used VGG-16 [12] and LeNet-5, we have also included these two networks. VGG-16 is a large network with a huge number of weights, thus it inherently has more redundancy.…”

Section: A Selected Dnnsmentioning

confidence: 99%

“…Previous works have studied faults in the DNN weights and PE register files [11], [14], [15] which can be protected with parity or ECC. Protecting the computational logic in the PE is more difficult, as it requires fault tolerance strategies that typically have high area costs, timing penalties and are architecture dependent.…”

Section: B Hardware Fault Modelmentioning

confidence: 99%

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MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators

Burel

Evans

Anghel

2021

2021 IEEE 27th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Deep Neural Networks (DNNs) are increasingly used in safety critical autonomous systems. In this paper, we present MOZART, a DNN accelerator architecture which provides fault detection and fault tolerance. MOZART is a systolic architecture based on the Output Stationary (OS) variant, as it is the one that inherently limits fault propagation. In addition, MOZART achieves fault detection with on-line functional testing of the Processing Elements (PEs). Faulty PEs are swiftly taken off-line with minimal classification impact. The implementation of our approach on Squeezenet results in a loss of accuracy of less than 3% in the presence of a single faulty PE, compared to 15-33% without mitigation. The area overhead for the test logic does not exceed 8%. Dropout during training further improves fault tolerance, without a priori knowledge of the faults.

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“…effect of weight perturbation on the network output [15]- [18]. Cheney [17] figured out that CNNs show surprising robustness to weight perturbations in the topper convolutional layers but fragileness in the bottom. In the application of safety critical tasks, such as self-driving, it is of great importance to acquaint the output changes of CNNs to weight perturbations, which will affect real time execution.…”

Section: Introductionmentioning

confidence: 99%

Study of Sensitivity to Weight Perturbation for Convolution Neural Network

2019

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Exploring underlying properties of a neural network contributes to pursuing its internal behavior and functionality. For convolution neural networks (CNNs), a sensitivity measure to weight perturbation is introduced in this paper to reflect the extent of the network output variation, which could evaluate the effect of the weights on the network. The sensitivity is defined as the mathematical expectation of absolute output variation due to weight perturbation with respect to all possible inputs. Assuming that the conditional distribution of input obeys the normal, the sensitivity is iteratively computed layer to layer until the entire network. Without loss of generality, the paper proposes an approximate algorithm to compute a theoretical sensitivity, which is actually a function of mapping between the network's output variation and its weight perturbation. The experimental results demonstrate the coincidence of the computed theoretical sensitivity with the simulated actual output variation of the network. Thus a criterion can be established to evaluate the influence of weights on CNNs' output.INDEX TERMS Convolutional neural network, sensitivity, weight perturbation.

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The Robustness of Modern Deep Learning Architectures against Single Event Upset Errors

Cited by 27 publications

References 23 publications

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators

Study of Sensitivity to Weight Perturbation for Convolution Neural Network

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