The RC compiler for the DTN dataflow computer

Veen, Arthur H.; Born, Reiner van den

doi:10.1016/0743-7315(90)90033-l

Cited by 12 publications

(3 citation statements)

References 9 publications

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“…CASH could in principle be used to target a traditional dataflow machine. To our knowledge, none of the other efforts to translate C for execution on dataflow machines (e.g., [105]) reached completion.…”

Section: Related Workmentioning

confidence: 99%

Spatial computation

et al. 2004

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This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures. SC program implementations are completely distributed, with no centralized control. SC circuits are optimized for wires at the expense of computation units.In this paper we investigate a particular implementation of SC: ASH (Application-Specific Hardware). Under the assumption that computation is cheaper than communication, ASH replicates computation units to simplify interconnect, building a system which uses very simple, completely dedicated communication channels. As a consequence, communication on the datapath never requires arbitration; the only arbitration required is for accessing memory. ASH relies on very simple hardware primitives, using no associative structures, no multiported register files, no scheduling logic, no broadcast, and no clocks. As a consequence, ASH hardware is fast and extremely power efficient.In this work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs;(2) that distributed computation is in some respects fundamentally different from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33% slower in performance (3.5x worst-case).

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Section: Related Workmentioning

confidence: 99%

Spatial computation

et al. 2004

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“…The PDW is different than the PDG in that it can not only be interpreted but that it can be interpreted under control-, data-and demanddriven disciplines. The only structure that is even similar to the PDW is the "demand graph ''4 used in the RC compiler for the DTN Dataflow Computer [41 ]. However, the demand graph is designed for data-driven execution only.…”

Section: The Program Dependence Web (Pdw)mentioning

confidence: 99%

Varying execution discipline to increase performance

Campbell¹,

Maccabe²

1993

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Supercomputers i also define a major frontier of computing technology. The familiar constraints of cost, physical size, and power consumption are put aside in favor of performance .... Future i'i gains in speed will require new architectures, such as systolic arrays, hypercubes, datai flow machines, and other large networks of processing elements. "-Peter J. Denning and George B. Adams IH, "Research Questions for Performance Analysis of Supercomputers." ([11], p.405

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“…More recent work [5] has defined a single-assignment intermediate form to which a compiler is to map Fortran programs for execution on dynamic dataflow architectures. In addition, work has been done in compiling C programs for a specialized dataflow architecture [17]. These efforts were not completely satisfactory; the inherent dependencies result in a low level of available parallelism that is not a good match for the fine-grained dataflow paradigm.…”

Section: Softwarementioning

confidence: 99%

Multithreaded computer systems

Papadopoulos¹,

Bohm²,

Dahbura³

et al.

Proceedings Supercomputing '92

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Multithreaded computer systems are parallel machines in which threads are sequentially executed code segments. Each processor has hardware support for quickly switching contexts among runnable threads. Other features include some form of data matching, split-phase memory accesses, and a dataflow-like regime for thread instantiation. They combine features of conventional von Neumann systems with those of fine-grained dataflow architectures.In this minisymposium three speakers address architectural principles and issues, examine approaches to providing implicitly parallel software for these machines, and give an industrial perspective that includes the potential wader influence of multithreaded computers.1063-9535/92 $3.00 0 1992 IEEE

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The RC compiler for the DTN dataflow computer

Cited by 12 publications

References 9 publications

Spatial computation

Spatial computation

Varying execution discipline to increase performance

Multithreaded computer systems

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