Spatial computation

Abstract

This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures. SC program implementations are completely distributed, with no centralized control. SC circuits are optimized for wires at the expense of computation units.In this paper we investigate a particular implementation of SC: ASH (Application-Specific Hardware). Under the assumption that computation is cheaper than communication, ASH replicates computation units to simplify interconnect, building a system which uses very simple, completely dedicated communication channels. As a consequence, communication on the datapath never requires arbitration; the only arbitration required is for accessing memory. ASH relies on very simple hardware primitives, using no associative structures, no multiported register files, no scheduling logic, no broadcast, and no clocks. As a consequence, ASH hardware is fast and extremely power efficient.In this work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs;(2) that distributed computation is in some respects fundamentally different from monolithic superscalar processors; and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33% slower in performance (3.5x worst-case).

Heterogeneous Latch-Based Asynchronous Pipelines

“…These kernels were synthesized using the CASH compiler [25,2] to target a [180nm/2V] ST Microelectronics standard cell library. After physical design, the circuit's timing was extracted using Synopsys Design Compiler (SDC) and simulated using Modelsim.…”

“…2. A set of benchmarks from the Mediabench suite [12] were processed by the CASH compiler [2,25] and synthesized as both a homogeneous D-latch implementation as well as a homogeneous SR-latch implementation. The kernels are listed in Table 1.…”

“…The kernels are listed in Table 1. The C function in the table was the input to the compiler, which translates the program to a predicated dataflow graph representation [2]. Each node in this graph is synthesized as a handshaking pipeline stage that includes a pipeline latch.…”

“…After pre-assigning these nodes, the top-level algorithm iterates over the remaining nodes looking for candidates that can use an SR-latch if they satisfy (2). In each iteration of the while loop in Lines 5-19, we find the node, v, which has the largest global slack on both its R v ↑ and R v ↓ events.…”

“…We have incorporated this optimization within CASH [2,25], a hardware compiler that synthesizes asynchronous fourphase bundled data handshake circuits from C programs. Experimental results from synthesizing several media processing kernels from the Mediabench [12] suite indicate that the proposed algorithm achieves the best energy-delay and energydelay-area properties when compared to homogeneous D-latch and homogeneous SR-latch implementations.…”