The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

Ghose, Saugata; Hsieh, Kevin; Boroumand, Amirali; Ausavarungnirun, Rachata; Mutlu, Onur

doi:10.1007/978-3-319-90385-9_5

Cited by 21 publications

(19 citation statements)

References 187 publications

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“…These proposals are known as computational RAM, intelligent RAM, processing in memory chips, intelligent memory systems, [22] - [31], etc. These merged memory/logic chips implement on-chip memory which allows high internal bandwidth, low latency, and high power efficiency, eliminating the need for expensive, high-speed inter-chip interconnects, [35]. This makes them suitable to perform computations which require high data throughput and stride memory accesses, such as FFT, multimedia processing, network processing, etc., [28].…”

Section: Current Statementioning

confidence: 99%

FPGA Implementation of RISC-based Memory-centric Processor Architecture

Efnusheva¹

2019

IJACSA

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The development of the microprocessor industry in terms of speed, area, and multi-processing has resulted with increased data traffic between the processor and the memory in a classical processor-centric Von Neumann computing system. In order to alleviate the processor-memory bottleneck, in this paper we are proposing a RISC-based memory-centric processor architecture that provides a stronger merge between the processor and the memory, by adjusting the standard memory hierarchy model. Indeed, we are developing a RISC-based processor that integrates the memory into the same chip die, and thus provides direct access to the on-chip memory, without the use of general-purpose registers (GPRs) and cache memory. The proposed RISC-based memory-centric processor is described in VHDL and then implemented in Virtex7 VC709 Field Programmable Gate Array (FPGA) board, by means of Xilinx VIVADO Design Suite. The simulation timing diagrams and FPGA synthesis (implementation) reports are discussed and analyzed in this paper.

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Section: Current Statementioning

confidence: 99%

FPGA Implementation of RISC-based Memory-centric Processor Architecture

Efnusheva¹

2019

IJACSA

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“…In this paper, we explore two new approaches to enabling PIM in modern systems. The first approach only minimally changes memory chips to perform simple yet powerful common operations that the chip is inherently efficient at performing [12,13,15,22,23,60,73,[87][88][89][90][91][92][93]. Such solutions take advantage of the existing memory design to perform bulk operations (i.e., operations on an entire row of DRAM cells), such as bulk copy, data initialization, and bitwise operations [13,[88][89][90][91].…”

Section: Introductionmentioning

confidence: 99%

Enabling Practical Processing in and near Memory for Data-Intensive Computing

Mutlu

Ghose

Gómez-Luna

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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Modern computing systems suffer from the dichotomy between computation on one side, which is performed only in the processor (and accelerators), and data storage/movement on the other, which all other parts of the system are dedicated to. Due to this dichotomy, data moves a lot in order for the system to perform computation on it. Unfortunately, data movement is extremely expensive in terms of energy and latency, much more so than computation. As a result, a large fraction of system energy is spent and performance is lost solely on moving data in a modern computing system.In this work, we re-examine the idea of reducing data movement by performing Processing in Memory (PIM). PIM places computation mechanisms in or near where the data is stored (i.e., inside the memory chips, in the logic layer of 3D-stacked logic and DRAM, or in the memory controllers), so that data movement between the computation units and memory is reduced or eliminated. While the idea of PIM is not new, we examine two new approaches to enabling PIM: 1) exploiting analog properties of DRAM to perform massively-parallel operations in memory, and 2) exploiting 3D-stacked memory technology design to provide high bandwidth to in-memory logic. We conclude by discussing work on solving key challenges to the practical adoption of PIM.

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“…Even though the idea seems as simple, this combination requires special fabrication in-chip manufacturing. The architecture targets to combine the processor logic with a stack of through-silicon-via (TSV) bonded memory die [6,7]. The logical core of the memory system is a kind of single instruction multiple data (SIMD) processor where the different memory portions are directly connected to different cores, thus increasing the overall system bandwidth.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

et al. 2019

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Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

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The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

Cited by 21 publications

References 187 publications

FPGA Implementation of RISC-based Memory-centric Processor Architecture

FPGA Implementation of RISC-based Memory-centric Processor Architecture

Enabling Practical Processing in and near Memory for Data-Intensive Computing

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

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