An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Yantır, Hasan Erdem; Guo, Wenzhe; Eltawil, Ahmed M.; Kurdahi, Fadi; Salama, Khaled N.

doi:10.3390/mi10080509

Cited by 17 publications

(9 citation statements)

References 46 publications

(51 reference statements)

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“…At that point, a truly in-memory implementation of these applications on APs can provide more benefits than GPU-based implementations. Many studies in the literature prove that AP-based implementations of data-intensive applications have superior performance than the traditional correspondences [20,[40][41][42][43], including the applications that has processing flow similar to stencil codes like fast Fourier Transform (FFT) [44]. Therefore, it is obvious that another memory-bound application of the stencil code can get a benefit, which is the main idea of this study.…”

Section: Stencil Codesmentioning

confidence: 96%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

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Section: Stencil Codesmentioning

confidence: 96%

Efficient Acceleration of Stencil Applications through In-Memory Computing

2020

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“…APs have been explored for many applications such as matrix multiplication [11], [12], fast Fourier transform (FFT) [13], discrete Fourier transform (DCT) and video application [43], DNA sequence alignment [14], stencil applications [44], convolution operation [9], solution of path problems [45], optimum branchings [46], databases applications [47] and computer vision [48]. The old applications need to be revisited and re-evaluate under the new AP design approaches and technologies besides exploring new applications that could benefit from the AP.…”

Section: B Promising Applicationsmentioning

confidence: 99%

In-memory Associative Processors: Tutorial, Potential, and Challenges

Fouda¹,

Yantır²,

Eltawil³

et al. 2022

Preprint

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In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which eliminates the need for memory-processor communications. Hence, orders of magnitude speedup could be achieved especially with data-intensive applications. Associative processors (APs) were proposed since the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, We overview the functionalities and recent trends of APs in addition to the implementation of each Content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges and future directions are discussed.

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“…For this reason, their best usage is in applications that have an inherent SIMD (single-instruction multiple-data) computational pattern. Fast Fourier transform (FFT) [15], DNA sequence alignment [16], stencil [17], and matrix multiplication [18], [19] are some example applications that can benefit from AP. In an analogy, APs can be considered as a next step on the path of the CPU (central processing unit) to GPU (graphical processing unit) transformation.…”

Section: Content Addressable Memorymentioning

confidence: 99%

“…On the other hand, if the bit is logic-0, it simply skips all the write cycles since there will be no match at the end of a compare operation. This operation is crucial for many applications such as FFT, Fast Walsh-Hadamard transform, etc., when the multiplier is variable through the CAM rows [13], [15]. On the other hand, in CNNs, the same weights are applied to a frame during a convolution operation by performing constant multiplication.…”

Section: Constant Multiplication and Bit-level Sparsitymentioning

confidence: 99%

IMCA: An Efficient In-Memory Convolution Accelerator

Yantır

Eltawil

Salama

2021

IEEE Trans. VLSI Syst.

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Traditional convolutional neural network (CNN) architectures suffer from two bottlenecks; computational complexity and memory access cost. In this study, an efficient in-memory convolution accelerator (IMCA) is proposed based on associative in-memory processing to alleviate these two problems directly. In the IMCA, the convolution operations are directly performed inside the memory as in-place operations. The proposed memory computational structure allows for a significant improvement in computational metrics, namely, TOPS/W. Furthermore, due to its unconventional computation style, the IMCA can take advantage of many potential opportunities such as constant multiplication, bit-level sparsity, and dynamic approximate computing, which, while supported by traditional architectures, require extra overhead to exploit, thus reducing any potential gains. The proposed accelerator architecture exhibits a significant efficiency in terms of area and performance, achieving around 0.65 GOPS and 1.64 TOPS/W at 16-bit fixed-point precision with an area less than 0.25 mm 2 .

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An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Cited by 17 publications

References 46 publications

Efficient Acceleration of Stencil Applications through In-Memory Computing

Efficient Acceleration of Stencil Applications through In-Memory Computing

In-memory Associative Processors: Tutorial, Potential, and Challenges

IMCA: An Efficient In-Memory Convolution Accelerator

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