In-memory Associative Processors: Tutorial, Potential, and Challenges

Abstract

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which eliminates the need for memory-processor communications. Hence, orders of magnitude speedup could be achieved especially with data-intensive applications. Associative processors (APs) were proposed since the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, We overview the functionalities and recent trends of APs in addition to the implementation of each Content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges and future directions are discussed.

DT2CAM: A Decision Tree to Content Addressable Memory Framework

“…IMC architectures are gaining momentum for ML applications for they eliminate the memory wall, a known drawback in von Neumann architectures [21]. Ternary Content Addressable Memories (TCAMs), which perform massively parallel search operations, are considered one realization of IMC architectures that have proven to boost performance in terms of energy and latency [22]- [26].…”