The power of communication: Energy-efficient NOCS for FPGAS

Abstract

Integrating networks-on-chip (NoCs) on FPGAs can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large "hard" blocks such as high-speed I/O interfaces. We propose mixed and hard NoCs that add less than 1% area to large FPGAs and run 5-6× faster than the soft NoC equivalent. A detailed power analysis, per NoC component, shows that routers consume 14× less power when implemented hard compared to soft, and whether hard or soft most of the router's power is consumed in the input modules for buffering. For complete systems, hard NoCs consume less than 6% (and as low as 3%) of the FPGA's dynamic power budget to support 100 GB/s of communication bandwidth. We find that, depending on design choices, hard NoCs consume 4.5-10.4 mJ of energy per GB of data transferred. Surprisingly, this is comparable to the energy efficiency of the simplest traditional interconnect on an FPGA -soft point-to-point links require 4.7 mJ/GB. In many designs, communication must include multiplexing, arbitration and/or pipelining. For all these cases, our results indicate that a hard NoC will be more energy efficient than the conventional FPGA fabric.

Design guidelines for embeded NoCs on FPGAs

“…Kuon and Rose [6] compared between FPGA and ASIC using different benchmarks. Abdelfattah and Betz, made that comparison [7], [8] on router's sub-modules level using ASIC-specific router. In [9] a comparative review between FPGA-specific NoC and ASIC-specific one has been [4] covered.…”

“…We make a similar comparison to [7] and [8] for SoftHard utilization using FPGA-specific design CONNECT to provide design suggestions of which modules are suitable to be reconfigurable or to be harden, and give best design decisions for FPGA-specific router's sub-modules. Also to investigate whether the soft implementation of FPGA-specific NoC would give better results than ASIC-specific NoC or not.…”

Efficient and programmable ethernet switching with a NoC-enhanced FPGA

“…Since 10 6-LUTs fit into Stratix LABs, we also assume that there are always exactly 10 LUTs per LAB. 4 Our HNS switch configurations consume only 2.1% of the LUT area available, and little to no registers. When compared to the FPGA implementation of the MDN switch [19], the HNS consumes 6.9×-8.4× less area.…”

“…The hard NoC provides a fixed mesh topology and uses no programmable interconnect, thus easing the design and routing of the circuit logic and providing the fastest and most area-and power-efficient design [4]. The mixed NoC has the advantage of flexible, programmable topologies.…”

Dodec: Random-Link, Low-Radix On-Chip Networks

“…For example, consider 9 metal layers available in TSMC 65nm technology, 2 ⇠ 6 layers might be reserved for local wiring, clock and power; we only need 2 layers to freely route link wires -one for horizontal and one for vertical wires. Previous work [27] uses a 1.2um wide bit line (0.6um width with 0.6 spacing) to meet 1GHz timing. Therefore a typical 64-bit wide bidirectional link has a width of 153.6um.…”