Efficient and programmable ethernet switching with a NoC-enhanced FPGA

2017 IEEE International Conference on Communications (ICC)

2017

Abstract-Scaling-up Data Center Networks (DCNs) should be done at the network level as well as the switching elements level. The glaring reason for this, is that switches/routers deployed in the DCN can bound the network capacity and affect its performance if improperly chosen. Many multistage switching architectures have been proposed to fit for the next-generation networking needs. However all of them are either performance limited or too complex to be implemented. Targeting scalability and performance, we propose the design of a large-capacity switch in which we affiliate a multistage design with a Networkson-Chip (NoC) design. The proposal falls into the category of buffered multistage switches. Still, it has a different architectural aspect and scheduling process. Dissimilar to common point-topoint crossbars, NoCs used at the heart of the three-stage Closnetwork allow multiple packets simultaneously in the modules where they can be adaptively transported using a pipelined scheduling scheme. Our simulations show that the switch scales well with the load and size variation. It outperforms a variety of architectures under a range of traffic arrivals.

Section: B Network-on-chip For Packet Switching Fabricsmentioning

confidence: 99%

High-capacity clos-network switch for data center networks

2017 IEEE International Conference on Communications (ICC)

2017

“…In 2010, the Multidirectional NoC (MDN) packet-switch was proposed as an extension to UDN [9]. More recent results [10] discussed a possible implementation of a crossbar fabric using NoCenhanced FPGA, and evaluated its performance for various routing algorithms. In [8], Karadeniz et al suggested one stage packet switch with NoC fabric.…”

Section: Related Workmentioning

confidence: 99%

A scalable packet-switch architecture based on OQ NoCs for data center networks

2017

Computer Networks

Data Center switches need guarantee high throughput, resiliency and scalability for large-scale networks with constantly floating requirements. Multistage packet switches have been a pervasive solution to implement high-capacity Data Center Networks (DCNs) switches and routers. Yet, classical multistage switching architectures with their Space-Memory variants have shown limited performance. Most proposals prove either too complex to implement or not cost effective. In this paper, we present a highly scalable packet-switch for the DCN environment, in which we exploit the Network-on-Chip (NoC) design paradigm to replace the single-hop crossbars with multi-hop Switching Elements (SEs). In particular, we describe a three-stage switch with Output-Queued Unidirectional NoCs (OQ-UDN) in the central stage of the Clos-network. The design has several advantages over conventional multistage switches. First, it uses a simple Round-Robin (RR) packet dispatching scheme and avoids the need for complex and costly input modules. Besides, it offers better load balancing, a pipelined scheduling and more path-diversity. We assess the performance of the switch in terms of throughput, end-to-end latency and blocking probability using Markov chain analysis, and we propose an analytical model that integrates the various design parameters. Through extensive simulations, we show that the switching architecture achieves high performance under different types of traffic, and that both the analytical and experimental results correlate over wide range of evaluation settings.

“…In 2010, the Multidirectional NoC (MDN) packet switch was proposed as an extension to UDN [11]. More recent results [12] discussed a possible implementation of a single-stage crossbar fabric using NoC-enhanced FPGA and evaluated its performance for various routing algorithms. In [10], Karadeniz et al suggested a single-stage switch with Networks-on-Chip fabric.…”

Section: Related Workmentioning

confidence: 99%

A scalable packet-switch based on output-queued NoCs for data centre networks

2016 IEEE International Conference on Communications (ICC)

2016

Abstract-The switch fabric in a Data-Center Network (DCN) handles constantly variable loads. This is stressing the need for high-performance packet switches able to keep pace with climbing throughput while maintaining resiliency and scalability. Conventional multistage switches with their space-memory variants proved to be performance limited as they do not scale well with the proliferating DC requirements. Most proposals are either too complex to implement or not cost effective. In this paper, we present a highly scalable multistage switching architecture for DC switching fabrics. We describe a three-stage Clos packet-switch fabric with Output-Queued Unidirectional NoC (OQ-UDN) modules and Round-Robin packets dispatching scheme. The proposed OQ Clos-UDN architecture avoids the need for complex and costly input modules and simplifies the scheduling process. Thanks to a dynamic packets dispatching and the multi-hop nature of the UDN modules, the switch provides load balancing and path-diversity. We compared our proposed architecture to state-of-the art previous architectures under extensive uniform and non-uniform DC traffic types. Simulations of various switch settings have shown that the proposed OQ Clos-UDN outperforms previous proposals and maintains high throughput and latency performance.