2016 IEEE International Reliability Physics Symposium (IRPS) 2016
DOI: 10.1109/irps.2016.7574573
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The physical mechanism investigation between HK/IL gate stack breakdown and time-dependent oxygen vacancy trap generation in FinFET devices

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Cited by 10 publications
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“…Because both interface traps and oxide traps can degrade ∆V th while only the interface traps can degrade SS, the drop of ∆SS(i)/∆V th (i) with time in FinFET as shown in Figure 7 indicates that both interface traps and oxide traps are generated [29]. By applying SILC spectrum technique [74], two types of oxide traps are identified in the HCI process, as shown in [31].…”
Section: Trap Type In Finfetmentioning
confidence: 99%
“…Because both interface traps and oxide traps can degrade ∆V th while only the interface traps can degrade SS, the drop of ∆SS(i)/∆V th (i) with time in FinFET as shown in Figure 7 indicates that both interface traps and oxide traps are generated [29]. By applying SILC spectrum technique [74], two types of oxide traps are identified in the HCI process, as shown in [31].…”
Section: Trap Type In Finfetmentioning
confidence: 99%