2018 Conference on Design of Circuits and Integrated Systems (DCIS) 2018
DOI: 10.1109/dcis.2018.8681492
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Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms

Rui Zhang
1
,
Kexin Yang
2
,
Taizhi Liu
3
et al.
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Cited by 3 publications
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A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Zhang
1
,
Liu
2
,
Yang
3
et al. 2019
Microelectronics Reliability
4
0
3
0
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A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Zhang
1
,
Liu
2
,
Yang
3
et al. 2019
Microelectronics Reliability
4
0
3
0
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CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration

Zhang
1
,
Liu
2
,
Yang
3
et al. 2022
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
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7
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Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation

Wu
1
,
Yang
2
,
Hsu
3
et al. 2020
IEEE Trans. VLSI Syst.
2
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