A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Zhang, Rui; Liu, Zhaocheng; Yang, Kexin; Liu, Taizhi; Cai, Wenshan; Milor, Linda

doi:10.1016/j.microrel.2019.113486

Cited by 4 publications

(3 citation statements)

References 19 publications

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“…Compared with the traditional aging detection and prediction methods, this method sends an alarm signal before the circuit aging phenomenon, which avoids the disastrous consequences of aging. Due to the existence of aging mechanism, time delay can detect specific structures, so an aging prediction method is proposed [8][9]. The designed prediction structure (sensor) will collect a large number of aging information of different paths at different aging speeds.…”

Section: Integrated Circuit Aging Prediction Methods 21 Identificatio...mentioning

confidence: 99%

Design of IC aging prediction method based on logic gate type

MENG

2023

Second International Conference on Electronic Information Technology (EIT 2023)

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The aging of digital integrated circuits will have a certain [impact on the accuracy and reliability of circuits, and even pose a certain threat to the safety of circuits. To solve this problem, an IC aging prediction design method based on logic gate type is proposed. The aging characteristics of IC structure are identified by logic gate type technology, the aging degree index and evaluation algorithm of IC are standardized, and the aging prediction of IC is realized. Finally, experiments show that the IC aging prediction method based on logic gate type has high accuracy and reliability in practical application, and fully meets the research requirements.

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Section: Integrated Circuit Aging Prediction Methods 21 Identificatio...mentioning

confidence: 99%

Design of IC aging prediction method based on logic gate type

MENG

2023

Second International Conference on Electronic Information Technology (EIT 2023)

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“…The traditional reaction-diffusion (R-D) model attributes the cause of NBTI to the fact that the holes of the reverse layer of the PMOS tube are thermally excited under high temperature negative gate pressure and tunnel to the silicon/silica interface [8] , due to the presence of a large number of Si-H bonds at the interface, the holes in the channel at this time break the Si-H bond, due to the instability of the H atom, it diffuses to the gate and forms an interface trap, which is the increase in gate bias required for PMOS conduction. This is manifested as a negative drift of the device threshold voltage [9] .…”

Section: The Negative Bias Temperature Instability Effectmentioning

confidence: 99%

Study on performance degradation of static random access memory cells

Shen,

Liu,

2024

Ninth International Symposium on Sensors, Mechatronics, and Automation System (ISSMAS 2023)

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Static random access memory (SRAM) is a high-speed memory, which will produce performance degradation with the increase of use time, and the current research mostly analyzes its degradation process from an experimental point of view, but the correlation between basic circuits and components is insufficient. Starting from the physical degradation effect of transistors in SRAM unit circuits, this paper simulates the circuit-level characteristics of SRAM unit circuits to simulate their performance degradation, forming a complete research system from principle to phenomenon, and finding a new path for studying the circuit-level health monitoring method of SRAM performance degradation.

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“…Although technology scaling enables integrated circuits (ICs) with higher density and better performance, it is still faced with serious vulnerability to various aging mechanisms appearing from front-end to back-end [1][2][3][4][5][6][7][8][9][10]. These aging mechanisms include Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN), Gate-Oxide Breakdown (GOBD) at the front-end, Middle-of-line (MOL) time-dependent dielectric breakdown (TDDB), Back-end-of-line (BEOL) TDDB, and Electromigration (EM).…”

Section: Introductionmentioning

confidence: 99%

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

2022

Self Cite

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The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.

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A library based on deep neural networks for modeling the degradation of FinFET SRAM performance metrics due to aging

Cited by 4 publications

References 19 publications

Design of IC aging prediction method based on logic gate type

Design of IC aging prediction method based on logic gate type

Study on performance degradation of static random access memory cells

Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects

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