The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

Weiss, D.; Wuu, John; Chin, V.

doi:10.1109/jssc.2002.802354

Cited by 42 publications

(15 citation statements)

References 5 publications

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“…Moreover, the number and the location of failures due to process variation changes depending on operating condition (e.g., supply voltage and frequency), which cannot be handled by any static technique such as row/column redundancy. Error correcting code (ECC) [7], [8] employed in existing design to correct transient faults (soft error), can also be used to correct failures due to process variation. However, ECC can correct only a single-error, and hence, will not be sufficient in tolerating a number of failures due to process variation.…”

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confidence: 99%

A process-tolerant cache architecture for improved yield in nanoscale technologies

Agarwal

Paul

Mahmoodi

et al. 2005

IEEE Trans. VLSI Syst.

176

120

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Abstract-Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters.In this paper, we analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under inter = intra = 30 mV.

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mentioning

confidence: 99%

A process-tolerant cache architecture for improved yield in nanoscale technologies

Agarwal

Paul

Mahmoodi

et al. 2005

IEEE Trans. VLSI Syst.

176

120

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“…Still, we recommend and simulate a sequential access to these arrays for two reasons. One is that the SBC is oriented to non-first level caches, where both arrays are often accessed sequentially because in those caches the tag-array latency is much shorter than the dataarray one, and the sequential access is much more energyefficient than the parallel one [5] [17]. The other is that since the SBC may lead to second searches, the corresponding parallel data-array accesses would further increase the waste of energy.…”

Section: Discussionmentioning

confidence: 99%

Adaptive line placement with the set balancing cache

Rolan

Fraguela

Doallo

2009

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture

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Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is the non-uniform distribution of the memory accesses on the cache sets. Its consequence is that while some cache sets may have working sets that are far from fitting in them, other sets may be underutilized because their working set has fewer lines than the set. In this paper we present a technique that aims to balance the pressure on the cache sets by detecting when it may be beneficial to associate sets, displacing lines from stressed sets to underutilized ones. This new technique, called Set Balancing Cache or SBC, achieved an average reduction of 13% in the miss rate of ten benchmarks from the SPEC CPU2006 suite, resulting in an average IPC improvement of 5%.

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“…For instance, the IBM POWER4 architecture [4] has a 1.5MB L2 cache organized as three slices shared among its two processor cores; the IBM POWER5 has a 1.875MB L2 cache with a 36MB off-chip L3 [5]; the Intel Itanium [6] has a three-level, on-chip cache with combined capacity of 3MB; and the Intel Core i7 (Nehalem) has a shared L3 inclusive cache of 8MB [7]. As the complexity of on-chip caches increases, the need to reduce miss rates grows in importance, as does access time (even for L1 caches, single-cycle access times are no longer possible).…”

Section: Background and Related Workmentioning

confidence: 99%

Global management of cache hierarchies

Zahran

McKee

2010

Proceedings of the 7th ACM International Conference on Computing Frontiers

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Cache memories currently treat all blocks as if they were equally important, but this assumption of equally importance is not always valid. For instance, not all blocks deserve to be in L1 cache. We therefore propose globalized block placement, and we present a global placement algorithm for managing blocks in a cache hierarchy by deciding where in the hierarchy an incoming block should be placed. Our technique makes decisions by adapting to the access patterns of different blocks.The contributions of this paper are fourfold. First, we motivate our solution by demonstrating the importance of a globalized placement scheme. Second, we present a method to categorize cache block behavior into one of four categories. Third, we present one potential design exploiting this categorization. Finally, we demonstrate the performance of the proposed design. For the SPEC CPU benchmark suite, the scheme enhances overall system performance (IPC) by an average of 12% over a traditional LRU scheme, reducing traffic between the L1 and L2 caches by an average of 20% while using a table as small as 3KB.

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The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

Cited by 42 publications

References 5 publications

A process-tolerant cache architecture for improved yield in nanoscale technologies

A process-tolerant cache architecture for improved yield in nanoscale technologies

Adaptive line placement with the set balancing cache

Global management of cache hierarchies

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