Global management of cache hierarchies

Zahran, Mohamed; McKee, Sally A.

doi:10.1145/1787275.1787315

Cited by 14 publications

(5 citation statements)

References 20 publications

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“…A drawback of the aforementioned dead-block schemes is that they apply their predictions locally (mostly LLC). Global management has been investigated in the limited context of avoiding back-invalidation of hot data from the L1 cache as a consequence of eviction from the LLC (Zahran 2007;Jaleel et al 2010a;Tian et al 2013) and for optimizing placement of cache blocks in a twolevel cache hierarchy in uni-processor systems (Zahran and McKee 2010). In contrast, our work introduces global dead-block management, whereby dead-blocks are managed in a coordinated manner across the entire cache hierarchy.…”

Section: Related Workmentioning

confidence: 99%

Global Dead-Block Management for Task-Parallel Programs

Manivannan

Pericàs

Papaefstathiou

et al. 2018

ACM Trans. Archit. Code Optim.

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Task-parallel programs inefficiently utilize the cache hierarchy due to the presence of dead blocks in caches. Dead blocks may occupy cache space in multiple cache levels for a long time without providing any utility until they are finally evicted. Existing dead-block prediction schemes take decisions locally for each cache level and do not efficiently manage the entire cache hierarchy. This article introduces runtime-orchestrated global dead-block management, in which static and dynamic information about tasks available to the runtime system is used to effectively detect and manage dead blocks across the cache hierarchy. In the proposed global management schemes, static information (e.g., when tasks start/finish, and what data regions tasks produce/consume) is combined with dynamic information to detect when/where blocks become dead. When memory regions are deemed dead at some cache level(s), all the associated cache blocks are evicted from the corresponding level(s). We extend the cache controllers at both private and shared cache levels to use the aforementioned information to evict dead blocks. The article does an extensive evaluation of both inclusive and non-inclusive cache hierarchies and shows that the proposed global schemes outperform existing local dead-block management schemes.

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Section: Related Workmentioning

confidence: 99%

Global Dead-Block Management for Task-Parallel Programs

Manivannan

Pericàs

Papaefstathiou

et al. 2018

ACM Trans. Archit. Code Optim.

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“…The last-level cache (LLC) is usually at level 3, with level 2 being shared or private. How to manage this hierarchy of caches (SRAM) and memory (DRAM) [18], [19], [20], [21], [22], [23], [24]? A question looking for an answer is: as the number of cores increases, how will the cache hierarchy look like?…”

Section: P Erformancementioning

confidence: 99%

Multicore processors: Status quo and future directions

Zahran

2014

2014 10th International Computer Engineering Conference (ICENCO)

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Words like multicore, manycore, Moore's law end ing, have been around for more than a decade. How do these words describe the current status quo of computer architecture?How do they give a glimpse of the future? In this paper, we will present the status quo of the current multicore/manycore processors, and the expected future directions in light of several advances both in process technology and in system software.

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“…Garde et al [2008] analyzed the performance of global replacement policy by deconstructing the policy with reuse-distance analysis and evaluated it in a multicore inclusive cache hierarchy to show that the performance with global replacement policy was actually limited. Zahran and McKee [2010] proposed to make global cache placement decisions based on access patterns of dierent blocks. This technique is not designed for inclusive caches because it violates the inclusion property by placing some blocks only into higher-level caches but not the LLC.…”

Section: Related Workmentioning

confidence: 99%

Temporal-based multilevel correlating inclusive cache replacement

Tian

Khan

Jiménez

2013

TACO

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Inclusive caches have been widely used in Chip Multiprocessors (CMPs) to simplify cache coherence. However, they have poor performance compared with noninclusive caches not only because of the limited capacity of the entire cache hierarchy but also due to ignorance of temporal locality of the Last-Level Cache (LLC). Blocks that are highly referenced (referred to as hot blocks) are always hit in higher-level caches (e.g., L1 cache) and are rarely referenced in the LLC. Therefore, they become replacement victims in the LLC. Due to the inclusion property, blocks evicted from the LLC have to also be invalidated from higher-level caches. Invalidation of hot blocks from the entire cache hierarchy introduces costly off-chip misses that makes the inclusive cache perform poorly.Neither blocks that are highly referenced in the LLC nor blocks that are highly referenced in higherlevel caches should be the LLC replacement victims. We propose temporal-based multilevel correlating cache replacement for inclusive caches to evict blocks in the LLC that are also not hot in higher-level caches using correlated temporal information acquired from all levels of a cache hierarchy with minimal overhead. Invalidation of these blocks does not hurt the performance. By contrast, replacing them as early as possible with useful blocks helps improve cache performance. Based on our experiments, in a dual-core CMP, an inclusive cache with temporal-based multilevel correlating cache replacement significantly outperforms an inclusive cache with traditional LRU replacement by yielding an average speedup of 12.7%, which is comparable to an enhanced noninclusive cache, while requiring less than 1% of storage overhead.

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Global management of cache hierarchies

Cited by 14 publications

References 20 publications

Global Dead-Block Management for Task-Parallel Programs

Global Dead-Block Management for Task-Parallel Programs

Multicore processors: Status quo and future directions

Temporal-based multilevel correlating inclusive cache replacement

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