The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Abstract

We present here, for the first time, a fabrication technique that allows manufacturing scallop free,non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. TSVs are among major technology players in modern high-volume manufacturing as they enable 3D chip integration. However, the usual standardized TSV fabrication process has to deal with scalloping, an imperfection in the sidewalls caused by the deep reactive ion etching. The presence of scalloping causes stress and field concentration in the dielectric barrier, thereby dramatically impacting the following TSV filling step, which is performed by means of electrochemical plating. So, we propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called “Michelangelo”, we obtained an extremely well polishing of the TSV holes, by reaching atomic-level smoothness and a record aspect ratio of 28:1. The Michelangelo step will thus drastically reduce the footprint of 3D structures and will allow unprecedented efficiency in 3D chip integration.

Research of Vertical via Based on Silicon, Ceramic and Glass

“…Thereby, the TSV with small aperture and high aspect ratio is optimized to eliminate the "undercut" effect of aperture and meet the requirements of Park et al [53] optimized the RIE conditions of 100 W RF power and 30 SCCM (standard cubic centimeter/minute) for 30 min, which reduced the average depth of the scallops from 230 nm to 20 nm, resulting in a smooth profile of the sidewall groove. Frasca et al [54] reported that using 40% potassium hydroxide at 60 • C to form a Michelangelo step can prevent the formation of scallops, and conformal copper filling can control the critical aspect ratio phenomenon in DRIE by a micro-loading effect and RIE hysteresis. Gerlt et al [55] realized the reduction of RIE lag by adjusting the two-step process parameters of Bosch.…”

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

“…Park et al [23] reduced the average scallop depth by 91% from 230 to 20 nm by optimizing reactive ion etching (RIE) condition of 100W radio-frequency power and 30 SCCM (standard cubic centimeter per minute) of SF 8 for 30 min, resulting in smooth profiles of the sidewall trench. Frasca et al [24] reported that by forming a 'Michelangelo step' using 40% concentration of KOH at a temperature of 60 • C, it is possible to prevent scallop formation and perform conformal shape during Cu filling. The critical aspect ratio phenomenon in DRIE can be controlled using the microloading effect and RIE lag [25,26].…”