Research of Vertical via Based on Silicon, Ceramic and Glass

Tian, Wenchao; Wu, Shunjun; Li, Wenhua

doi:10.3390/mi14071391

Cited by 4 publications

(2 citation statements)

References 71 publications

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“…The Through Silicon Via (TSV) technology utilizes the shortest vertical interconnections to establish electrical connections between chips, significantly enhancing the data transfer speed and packaging density between chips. It is a core technology in 3D packaging and provides a viable pathway for 3D integration [1][2][3][4][5][6]. In recent years, with the continuous increase in chip interconnect density, research on the reliability issues of TSV-metal lines has also deepened.…”

Section: Introductionmentioning

confidence: 99%

Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process

Gong,

Xie,

Chen

et al. 2023

Crystals

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The combined use of Through Silicon Via (TSV) and metal lines, referred to as TSV-metal lines, is an essential structure in three-dimensional integrated circuits. In-depth research into the electromigration failure mechanism of TSV and the microstructure evolution can serve as theoretical guidance for optimizing three-dimensional stacking. This article conducted electromigration experiments on TSV-metal line structural samples at current densities of 1.0 × 105 A/cm2, 5 × 105 A/cm2, and 1 × 106 A/cm2. Additionally, Electron Back Scattered Diffraction (EBSD) technology was employed to systematically investigate the microstructural evolution of the TSV-metal line structure profiles before and after the application of electrical testing. The results indicate that the current induces a change in the crystal orientation at the TSV-metal interface (TSV/metal interface) and the bottom metal line. This phenomenon notably depends on the initial angle between the grain orientation and the current flow direction. When the angle between the current direction and the grain orientations [001] and [010] is relatively large, the crystals are more likely to deviate in the direction where the angle between the grain orientation and the current is smaller. This is because, at this point, the current direction is precisely perpendicular to the <100> crystal plane family, where the atomic density is lowest, and the energy required for electron transport is minimal. Therefore, the current readily rotates in the direction of this crystal orientation. Before the electromigration tests, areas with a high level of misorientation were primarily concentrated at the TSV/metal interface and the corners of the TSV-metal line. However, these areas were found to be more prone to developing voids after the tests. It is conjectured that the high misorientation level leads to elevated stress gradients, which are the primary cause of cracking failures in the TSV-metal line. As the current density increases from 5 × 105 A/cm2 to 1 × 106 A/cm2, the electromigration failure phenomena in the TSV become even more severe.

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Section: Introductionmentioning

confidence: 99%

Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process

Gong,

Xie,

Chen

et al. 2023

Crystals

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“…With the rapid development of integrated circuits, semiconductor chips are ubiquitous. Therefore, the reliability of devices, especially in high-precision and military fields, has put forward higher requirements [1,2]. Packaging forms of semiconductor chips can be divided into plastic packaging, ceramic packaging, metal packaging, etc.…”

Section: Introductionmentioning

confidence: 99%

Study on Cavitation, Warpage Deformation, and Moisture Diffusion of Sop-8 Devices during Molding Process

Tian,

Zhang,

et al. 2023

Micromachines

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Plastic packaging has shown its advantages over ceramic packaging and metal packaging in lightweight, thin, and high-density electronic devices. In this paper, the reliability and moisture diffusion of Sop-8 (Small Out-Line Package-8) plastic packaging devices are studied, and we put forward a set of complete optimization methods. Firstly, we propose to improve the reliability of plastic packaging devices by reducing the amount of cavitation and warpage deformation. Structural and process factors were investigated in the injection molding process. An orthogonal experiment design was used to create 25 groups of simulation experiments, and Moldflow software was used to simulate the flow mode analysis. Then, the simulation results are subjected to range analysis and comprehensive weighted score analysis. Finally, different optimization methods are proposed according to different production conditions, and each optimization method can reduce cavitation or warpage by more than 9%. The moisture diffusion of the Sop-8 plastic packing devices was also investigated at the same time. It was determined that the contact surface between the lead frame and the plastic packaging material was more likely to exhibit delamination under the condition of MSL2 moisture diffusion because the humidity gradient was easily produced at the crucial points of different materials. The diffusion of moisture is related to the type of plastic packaging material and the diffusion path.

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Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging

Tian,

Li,

Dang

et al. 2024

Micromachines

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Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa.

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Research of Vertical via Based on Silicon, Ceramic and Glass

Cited by 4 publications

References 71 publications

Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process

Research on Crystal Structure Evolution and Failure Mechanism during TSV-Metal Line Electromigration Process

Study on Cavitation, Warpage Deformation, and Moisture Diffusion of Sop-8 Devices during Molding Process

Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging

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