The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric

Torii, Kazuyoshi; Shimamoto, Yasuhiro; Saito, Shinichi; Tonomura, Osamu; Hiratani, Masahiko; Manabe, Yoshiki; Caymax, Matty; Maes, Jan Willem

doi:10.1109/vlsit.2002.1015446

Cited by 23 publications

(25 citation statements)

References 5 publications

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“…Therefore, more Al O incorporation into gate dielectrics with n+ poly gate electrode doped by phosphorous cause more fixed charges in gate dielectrics [7]. Another main mechanism is a change in the coordination number of Al from six (octahedral) to four (tetrahedral) with thin SiO interface layer [8]. Tetrahedrally coordinated Al is believed the source of negative fixed charge in Al O .…”

Section: Resultsmentioning

confidence: 99%

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Bae¹,

Lee²,

Clark³

et al. 2003

IEEE Electron Device Lett.

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Thermally stable, high-quality ultrathin (EOT = 13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO 2 up to 900 C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.

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Section: Resultsmentioning

confidence: 99%

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Bae¹,

Lee²,

Clark³

et al. 2003

IEEE Electron Device Lett.

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“…The presence of a SiO 2 IL is often desired because it helps to alleviate the reduction in carrier mobility in the transistor channel due to interaction with the high-k dielectric. 5 However, the total EOT of the gate stack will therefore always consist of contributions from both the high-k layer and the IL. For scaled high-k gate stacks, the EOT contribution of the IL can become even more significant than the one from the high-k layer on top because of its lower k value ͑as a first approximation by a factor of k high-k /3.9͒.…”

Section: Improvement Of Complementary Metal Oxide Semiconductormentioning

confidence: 99%

Equivalent Oxide Thickness Reduction for High-k Gate Stacks by Optimized Rare-Earth Silicate Reactions

Elshocht

Adelmann

Lehnen

et al. 2009

Electrochem. Solid-State Lett.

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Equivalent oxide thickness ͑EOT͒ scaling still remains one of the main facilitators to increase transistor performance. The use of rare-earth ͑RE͒ elements has been shown to effectively increase permittivity of the gate-stack interfacial layer between substrate and high-k dielectric, reducing its EOT contribution. In this paper, we have studied the optimal RE-to-SiO 2 ratio using Dy 2 O 3 as a test case. Capacitance-voltage and leakage current-voltage measurements were performed on Pt-gated capacitors with a SiO 2 /Dy 2 O 3 /Sc-doped HfO 2 gate stack and varying ratios of Dy 2 O 3 to SiO 2 after a 1000°C anneal. Optimal EOT-leakage performance was found for a Dy 2 O 3 -to-SiO 2 ratio of ϳ0.5 to 0.6. Improvement of complementary metal oxide semiconductor ͑CMOS͒ transistor performance is largely driven by the scaling of the equivalent oxide thickness ͑EOT͒ of the gate dielectric. 1 To allow continued scaling, beyond the limitations of SiON gate dielectrics due to excessive gate leakage, Hf-based dielectric layers have been introduced in the gate stack. 2 Because of their higher permittivity ͑k value͒ compared to SiON, the dielectric layer can be made thicker while maintaining high capacitance values, i.e., without having to compromise with respect to the EOT. 3,4 In practice, there is typically a SiO 2 -like interfacial layer ͑IL͒ present between the high-k layer and the silicon substrate. The presence of a SiO 2 IL is often desired because it helps to alleviate the reduction in carrier mobility in the transistor channel due to interaction with the high-k dielectric. 5 However, the total EOT of the gate stack will therefore always consist of contributions from both the high-k layer and the IL. For scaled high-k gate stacks, the EOT contribution of the IL can become even more significant than the one from the high-k layer on top because of its lower k value ͑as a first approximation by a factor of k high-k /3.9͒. This implies that EOT scaling of thin stacks is more efficient by reducing the thickness ͑or more generally the EOT contribution͒ of the IL than that of the high-k layer.The IL that is present at the end of the CMOS device process can have different origins. First, a SiO 2 layer is often grown deliberately prior to the high-k deposition. This can be done to reduce the influence of the high-k dielectric on channel mobility or to accommodate the high-k deposition itself, as it has been shown that, for example, atomic layer deposition ͑ALD͒ HfO 2 by HfCl 4 /H 2 O needs a proper starting surface for optimal growth. 6,7 Next, depending on thickness and composition of the starting surface, the starting layer can further oxidize ͑thicken͒ during high-k growth. Especially for metallorganic chemical vapor deposition type depositions, this typically occurs because of the higher deposition temperatures as compared to, for example, ALD or physical vapor deposition. [8][9][10] Finally, even when the IL thickness can be controlled before and during high-k deposition, there is still the possibility of IL regrowth during h...

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“…The samples were then cleaned using the 3 As seen from Figs. 4.3(a) [77]. This observation is quite similar to that of Cheong et al [73] where they observed the negative charge in their atomic layer deposited (ALD) deposited As seen from Table 4.1, the negative charge on our AlN y :H/SiO 2 dielectric stack is lower than AlN x /SiO 2 .…”

Section: Process Detailssupporting

confidence: 87%

Development of process technology for fabrication of 4H-SiC silicon carbide schottky barrier diodes

Sudhakar¹

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In recent times, 4H-SiC has been at the center of power semiconductor device research due to its superior material properties such as large bandgap (E g ~3.26 eV), high breakdown electric field (E c ~3 MV/cm which is almost 10 times that of Si), high saturated electron velocity (~2.0×10 7 cm/s which is almost 2 times that in Si), high thermal conductivity (K ~4.9 W/cm.K) and most importantly ability to form a stable native oxide SiO 2. Schottky barrier diodes (SBDs) based on 4H-SiC offer superior dynamic performance (<20 nC reverse recovery charge for a 1200 V, 1A SBD), almost 100 times lower specific-on resistance compared to Si SBDs and PiN diodes. The higher bandgap results in much higher schottky barrier height compared to Si and GaAs resulting in extremely low leakage currents even at elevated temperatures (>300 o C operation). Edge termination and passivation is a critical technology for power devices to fully realize their voltage blocking potential. The objective of this research was to develop the process technology for fabrication of high voltage 4H-SiC SBDs. We decided to use a simple edge termination technique based on Field-Plate (FP) termination. The simplicity of FP termination lies in the fact that unlike other termination techniques such as guard rings, mesa and Junction Termination Extensions (JTE), it does not need high temperature ionimplantations. Such high temperature implantation requires the substrate to be maintained at 700-1000 o C during implantation. It also needs subsequent extreme high temperature anneals in excess of 1500 o C to reduce implantation damage. There are also design issues such as the need to optimize ring spacing. FP termination technique has long been a power horse of Si power device technology using thick SiO 2 field oxide and poly silicon as electrode overlapping the oxide. For past decade or so since its first application to SiC power device ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library XI 6.5.3 Electric Field profile of FP terminated 4H-SiC SBDs along the schottky edge with 2-step Breakdown………………………………. 6.6 Conclusions………………………………………………………………. 7. Conclusions and Recommendations for Future Work………………………… 7.1 Conclusions………………………………………………………………. 7.2 Recommendations for Future Work…………………………………….

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The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric

Cited by 23 publications

References 5 publications

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Equivalent Oxide Thickness Reduction for High-k Gate Stacks by Optimized Rare-Earth Silicate Reactions

Development of process technology for fabrication of 4H-SiC silicon carbide schottky barrier diodes

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