The low power design of SM4 cipher with resistance to differential power analysis

Niu, Yanbo; Jiang, Anping

doi:10.1109/isqed.2015.7085471

Cited by 12 publications

(8 citation statements)

References 4 publications

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“…Few studies have focused on achieving a low power consumption value, such as in References [19,20]. However, only one pipelined design is considered: either a full pipeline architecture (32 stages), such as in Reference [20], or a partial pipeline architecture (four stages), such as in Reference [19]. Examining different numbers of stages is not considered because they can affect the results.…”

Section: Related Workmentioning

confidence: 99%

“…Examining different numbers of stages is not considered because they can affect the results. Our work is difficult to be compared with works in References [19,20], as the design parameters and technology used are different, and it will not be a fair comparison. To the extent of our knowledge, this is the first research that concerns implementing and optimising the SM4 cipher in two main architectures: the iterative (scalar) and pipelined architectures, by varying the number of rounds in each one to determine the best design in terms of different performance metrics while focusing on the power/energy analysis.…”

Section: Related Workmentioning

confidence: 99%

“…Others have concentrated on implementing high throughput designs [8,[11][12][13][14][16][17][18]. Some authors have optimised the SM4 cipher for achieving low power consumption [19,20]. Power analysis and power attack implementations have been discussed [19,[21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

“…Some authors have optimised the SM4 cipher for achieving low power consumption [19,20]. Power analysis and power attack implementations have been discussed [19,[21][22][23][24]. Power/energy optimisation concerns have not been the main focus of the research.…”

Section: Introductionmentioning

confidence: 99%

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Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Abed

Jaffal

Mohd

et al. 2021

IET Circuits, Devices & Syst

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Information security is essential to ensure security of exchanged sensitive data in resource‐constrained devices (RCDs) because they are used widely in the Internet of things (IoT). The implementation of special ciphers is required in these RCDs, as they have many limitations and constraints, such as low power/energy dissipation, and require low hardware resources. The SM4 cipher is one of the common block ciphers, which can be easily implemented and offers a high level of security. The objective of this study is to determine the optimum field‐programmable gate array (FPGA) design for SM4 to facilitate reconfiguring the FPGA with an optimum design during operation. Various FPGA design options for SM4 ciphers are examined, and the performance metrics are modeled: power, energy, area, and speed. Scalar and pipelined designs with one or multiple hardware rounds are considered without altering the cipher algorithm. The results show that the best scalar implementation utilises less resources than the pipelined implementations by 7%. Alternatively, pipelined implementations perform better regarding speed and energy dissipation by 10 times and 40% of the scalar implementation, respectively. The pipeline implementations with eight or 16 rounds are optimum for continuous streams of data, and the two‐round design is the optimum design across ciphers.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Abed

Jaffal

Mohd

et al. 2021

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

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“…As the SM4 algorithm is mostly used in high-speed and resource constrained applications, it is very necessary to design and implement the compact circuit of SM4. As a standard cipher algorithm, SM4 has been widely used in the field of information security for its short build time and low memory requirements [1][2][3]. However, Differential Power Analysis (DPA), which has been developed in recent years, has brought great challenges to the security of SM4 circuits.…”

Section: Introductionmentioning

confidence: 99%

The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack

Fang

Zhang

et al. 2020

Electronics

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In order to achieve the purpose of defending against side channel attacks, a compact SM4 circuit was designed based on the mask and random delay technique, and the linear transformation module was designed with random insertion of the pseudo operation method. By analyzing the glitch data generated by the S-box of SM4 with different inputs, the security against glitch attacks was confirmed. Then, the DPA (Differential Power Analysis) was performed on the designed circuit. The key could not be successfully obtained even in the case of 100,000 power curves, so that the safety of SM4 against DPA is verified. Finally, using Synopsys DC (Design Compiler, Mountain View, CA94043DC, USA) to synthesize the designed circuit, the results show that the area of the designed circuit in the SMIC 0.18 process is 82,734 μm2, which is 48% smaller than results reported in other papers.

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A Very Compact Masked S-Box for High-Performance Implementation of SM4 Based on Composite Field

Bai

2017

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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The low power design of SM4 cipher with resistance to differential power analysis

Cited by 12 publications

References 4 publications

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation

The Design of Compact SM4 Encryption and Decryption Circuits That Are Resistant to Bypass Attack

A Very Compact Masked S-Box for High-Performance Implementation of SM4 Based on Composite Field

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