The limits of speculative trace reuse on deeply pipelined processors

Abstract

Abstract

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

“…Indeed, it can take many cycles after execution reaches the start of a trace before all inputs are available, which limits the benefits of trace reuse. Previous studies [14] show that only half of possible traces are reused in a non-speculative trace reuse architecture due to input values not being ready to be compared with stored traces. However, reusing only those traces allowed for an average speedup of 1.19 over an architecture without reuse.…”

“…System calls are not reused because they require a mode change in the processor status. Details on trace construction and reuse can be found in [14].…”

“…Confidence mechanisms [2] are employed to improve value prediction by restricting prediction of unpredictable values. Past work that explored the limits of value prediction with trace reuse has shown there is much potential for performance improvement [14].…”

“…Our past papers presented a study of how well RST can work in ideal conditions [14], while this paper describes and evaluates a feasible, constrained RST implementation. RST does both value speculation and trace reuse in a single, integrated mechanism that can be implemented in a superscalar pipeline with minimal complexity, as we show in this paper.…”

Value Predictors for Reuse through Speculation on Traces

“…We have previously described a novel technique, called Reuse through Speculation on Traces (RST), that combines reuse and prediction in an integrated mechanism [15,16,17]. In this scheme, traces that could not be reused by regular trace reuse due to the unavailability of inputs can be reused by predicting values for the missing inputs.…”