A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

Pilla, Maurı́cio L.; Childers, Bruce R.; Costa, A.T. da; França, Felipe M. G.; Navaux, Philippe

doi:10.1109/sbac-pad.2006.7

Cited by 8 publications

(7 citation statements)

References 20 publications

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“…DTM is a reuse technique that operates on traces of instructions and is often implemented on top of Von Neumann‐based superscalar architectures, with further studies that include speculative execution . Speculative execution often improves the reuse rate of traces, because it enables reuse based on speculative values for input operands.…”

Section: Related Workmentioning

confidence: 99%

“…20 DTM 10 is a reuse technique that operates on traces of instructions and is often implemented on top of Von Neumann-based superscalar architectures, [16][17][18][19][20][21][22][23][24] with further studies that include speculative execution. [25][26][27][28] Speculative execution often improves the reuse rate of traces, because it enables reuse based on speculative values for input operands. The DTM has also been implemented in a Java Virtual Machine, 29 enabling the memoization and reuse of dynamic traces of java bytecode.…”

Section: Related Workmentioning

confidence: 99%

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DF‐DTM: Dynamic Task Memoization and reuse in dataflow

Rouberte

Sena

Nery

et al. 2018

Concurrency and Computation

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Summary Instruction Reuse is a technique adopted in Von Neumann architectures that improves performance by avoiding redundant execution of instructions when the result to be produced can be obtained by searching an input/output memoization table for such instruction. Trace reuse can be applied to traces of instructions in a similar fashion. However, those techniques are yet to be studied in the context of the Dataflow model, which has been gaining traction in the high performance computing community due to its inherent parallelism. Dataflow programs are represented by directed graphs where nodes are instructions or tasks and edges denote data dependencies between tasks. This work presents Dataflow Dynamic Task Memoization (DF‐DTM), a technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF‐DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. Moreover, this paper evaluates how reuse rates can be affected by limiting subgraph size, memoization table size, task granularity, and problem size, showing that DF‐DTM can yield good reuse rates in more realistic environments.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

Rouberte

Sena

Nery

et al. 2018

Concurrency and Computation

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show abstract

“…DTM is a reuse technique, which operates on traces of instructions. Further reuse mechanisms have been proposed on top of DTM or inspired by it, including speculative execution for superscalar CPUs () and a Java Virtual Machine that is able to memoize and reuse dynamic traces of java bytecode. Speculative execution often improves the reuse rate of traces because it enables reuse based on speculative values for input operands.…”

Section: Related Workmentioning

confidence: 99%

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Marzulo

Sena

Nery

et al. 2018

Concurrency and Computation

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Summary In a program, there is usually a significant amount of instructions that are repeatedly executed with the same inputs during the execution. This redundancy allows the reuse of previous computations, potentially reducing the program execution time. The Dynamic Trace Memoization technique (DTM) was proposed to exploit the reuse of a dynamic sequence of redundant instructions for superscalar CPUs. This paper proposes the application of the DTM technique on a GPU architecture. We propose the DTM@GPU model that adapts the original DTM technique to the NVIDIA GPU architecture by introducing architectural modifications and the identification of different trace reuse styles in multithreaded environments. We investigate reuse opportunities in real‐world GPU applications and the potential performance gains. We also perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%.

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“…With this approach, they have achieved a speedup of 10% in a 16-wide, 6-stage superscalar architecture, with 128 KB of storage for the CDP. RST has higher overall speedups and requires less storage [17,19,20].…”

Section: Related Workmentioning

confidence: 99%

Decanting the Contribution of Instruction Types and Loop Structures in the Reuse of Traces

Coppieters¹,

Oliveira²,

França³

et al. 2017

Preprint

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Reuse has been proposed as a microarchitecture-level mechanism to reduce the amount of executed instructions, collapsing dependencies and freeing resources for other instructions. Previous works have used reuse domains such as memory accesses, integer or not floating point, based on the reusability rate. However, these works have not studied the specific contribution of reusing different subsets of instructions for performance. In this work, we analysed the sensitivity of trace reuse to instruction subsets, comparing their efficiency to their complementary subsets. We also studied the amount of reuse that can be extracted from loops. Our experiments show that disabling trace reuse outside loops does not harm performance but reduces in 12% the number of accesses to the reuse table. Our experiments with reuse subsets show that most of the speedup can be retained even when not reusing all types of instructions previously found in the reuse domain.

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A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

Abstract: Abstract

Cited by 8 publications

References 20 publications

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Decanting the Contribution of Instruction Types and Loop Structures in the Reuse of Traces

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