Value Predictors for Reuse through Speculation on Traces

Pilla, Maurı́cio L.; Navaux, Philippe; Childers, Bruce R.; Costa, A.T. da; França, Felipe M. G.

doi:10.1109/sbac-pad.2004.42

Cited by 6 publications

(8 citation statements)

References 39 publications

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“…DTM is a reuse technique, which operates on traces of instructions. Further reuse mechanisms have been proposed on top of DTM or inspired by it, including speculative execution for superscalar CPUs () and a Java Virtual Machine that is able to memoize and reuse dynamic traces of java bytecode. Speculative execution often improves the reuse rate of traces because it enables reuse based on speculative values for input operands.…”

Section: Related Workmentioning

confidence: 99%

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Marzulo

Sena

Nery

et al. 2018

Concurrency and Computation

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Summary In a program, there is usually a significant amount of instructions that are repeatedly executed with the same inputs during the execution. This redundancy allows the reuse of previous computations, potentially reducing the program execution time. The Dynamic Trace Memoization technique (DTM) was proposed to exploit the reuse of a dynamic sequence of redundant instructions for superscalar CPUs. This paper proposes the application of the DTM technique on a GPU architecture. We propose the DTM@GPU model that adapts the original DTM technique to the NVIDIA GPU architecture by introducing architectural modifications and the identification of different trace reuse styles in multithreaded environments. We investigate reuse opportunities in real‐world GPU applications and the potential performance gains. We also perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%.

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Section: Related Workmentioning

confidence: 99%

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Marzulo

Sena

Nery

et al. 2018

Concurrency and Computation

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“…They also provide a scheme to replay a frame in case an assertion fires, which signals a misprediction of an easily predictable branch which was promoted. In this way, they achieve a coarse granularity, enabling dynamic code optimizations during execution, and alongside the rollback mechanism, the opportunity for aggressive speculative techniques, such as value prediction and value reuse (PILLA et al, 2004). Although the framework is described, it is not explored in the paper.…”

Section: Code Behavior Detection and Usementioning

confidence: 99%

“…Although many other design points are becoming increasingly important, such as energy consumption, and others have been explored to some extent, such as value reuse (PILLA et al, 2004), branch prediction and memory access remain constant problems across decades. Therefore, it is of our interest to obtain information on the state-ofthe-art mechanisms used to treat or alleviate these issues.…”

Section: Hardware Design Opportunitiesmentioning

confidence: 99%

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level

Moreira

Alves

Koren³

2014

2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing

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“…Hardware approaches have been used to reuse results of long-latency alu operations [7,8,9,10,11] and compress functions or arbitrary sequences of instructions into a single memoized result [12,7,8,13,14,15,16,17,18]. Further studies were performed to analyze the effectiveness and propose solutions for instruction reuse in the hardware [19,20,21,22,23,24,25,26,27].…”

Section: Related Workmentioning

confidence: 99%

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

Long

Franklin

Biswas

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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-Parallelism is the key to continued performance scaling in modern microprocessors. Yet we observe that this parallelism can often contain a surprising amount of instruction redundancy. We propose to exploit this redundancy to improve performance and decrease energy consumption.We propose a multi-threading micro-architecture, Minimal Multi-Threading (MMT), that leverages register renaming and the instruction window to combine the fetch and execution of identical instructions between threads in SPMD applications. While many techniques exploit intra-thread similarities by detecting when a later instruction may use an earlier result, MMT exploits inter-thread similarities by, whenever possible, fetching instructions from different threads together and only splitting them if the computation is unique. With two threads, our design achieves a speedup of 1.15 (geometric mean) over a twothread traditional SMT with a trace cache. With four threads, our design achieves a speedup of 1.25 (geometric mean) over a traditional SMT processor with four-threads and a trace cache. These correspond to speedups of 1.5 and 1.84 over a traditional out-of-order processor. Moreover, our performance increases in most applications with no power increase because the increase in overhead is countered with a decrease in cache accesses, leading to a decrease in energy consumption for all applications.

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Value Predictors for Reuse through Speculation on Traces

Abstract: Reusing dynamic sequences of instructions-i.e., traces-improves

Cited by 6 publications

References 39 publications

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level

Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors

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