The influences of grain size distributions on thermal-stresses in Cu-TSV

Abstract

The dimensions of copper through-silicon vias (Cu-TSVs) have been shrunk to a microscopic scale, where the sizes of the copper grains are comparable to the vias, and thus the microstructure of the copper in the vias should be taken into consideration for reliability predictions. This paper focuses on the influences of the grain size distributions on the thermal-mechanical behaviors of the TSVs. Copper grains in TSVs are generated by both the Voronoi algorithm and a phase field method. The equations relating the yield stress and the Young's modulus with respect to grain size are derived from experimental data. Two different boundary conditions are applied to the TSV models in the thermal mechanical simulations and the thermal stresses of the microstructural models are calculated using the finite element method (FEM). The results from the microstructural models are then compared with the results from the reference model which ignores the grain structures. The results show that the copper grains can influence the thermal stresses in the via with negligible effects on other regions of the TSV. Smaller grains result in higher stresses, and the increase in stress can be as high as 30 MPa. The influence of the grain size distribution on thermal stress depends on the location of the grains as well as the applied boundary conditions. The grains with similar sizes in different grain structures can exhibit a difference in thermal stress around 10 MPa, whereas a difference in the boundary condition can lead to a completely different stress distribution.

Thermal stresses around TSV structure in stacked Si chips

“…Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [1]- [9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate.…”

Thermal stresses at interfaces in a semiconductor package

“…However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied by the chips. Recently, 3D packaging technology has been investigated to reduce size of devices and to improve performance of semiconductor devices [1][2][3][4][5][6][7][8][9][10][11]. In particular, study on TSV (through silicon via) has been developed for stacked structure of semiconductor chips.…”