Thermal stresses at interfaces in a semiconductor package

Abstract

INTRODUCTIONIn conventional SiP (System in Package), several semiconductor chips had been 2D arranged in an interposer and a mother board. However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied by the chips. Recently, 3D packaging technology has been investigated to reduce size of devices and to improve performance of semiconductor devices [1][2][3][4][5][6][7][8][9][10][11]. In particular, study on TSV (through silicon via) has been developed for stacked structure of semiconductor chips. TSVs are electrodes which are through semiconductor chip and conduct electrical signals between stacked semiconductor chips. TSV technology enables faster signal communication and downsizing of devices. 3D stacked structure developed by ASET (Association of Super-Advanced Electronics Technologies) and its enlarged structure are shown in Fig. 1 [10]. Many Cu-TSV are formed in three stacked semiconductor chips and SiO 2 -insulator and resin are formed as shown in its enlarged structure around TSV structure. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon and devices are broken by thermal stress which is depend on temperature increment. In case of reflow process, fracture of silicon and devices are also reported. In case of 3D-SiP, higher stresses are generated at interfaces and corner of electrical parts in globally and of materials in locally due to warp and mismatch of CTE (coefficient of thermal expansion) of materials. Therefore simulations which are focused on global area and local area are necessary for more accurate evaluation of fracture phenomena of 3D stacked package.In this study, we focused on fracture in global area of 3D stacked package and inelastic thermal stress simulations are performed under thermal conditions of power ON/OFF of device and of reflow process at 260 deg. C. Fig. 2. Quarter region is modeled and used in this study because of symmetry of the package. At center of the model, 3D stacked SiP is arranged. It is assumed that four Si chips were stacked in 3D SiP. Normally, Si chip was formed by two layers of TSV layer and bump layer, and TSV layer and bump layer were formed by many materials. However, TSV layer and bump layer were simplified as plates. Totally, 8 layers are modeled as 3D stacked SiP. SHAPE OF MODEL Scheme of simulation model was shown inIn center part of the model, 3D SiP was arranged on Silicon interposer. Silicon interposer was on the Cu-heat sink. Dimension of heat sink is 27.5 mm square and thickness is 1 mm. Organic interposer is arranged on the edge part of silicon interposer. Dimension of organic interposer is 27.5 mm square and thickness is 1 mm and 3.5 mm square in its center part is removed as shown Fig. 2. Dimension of silicon interposer is 5 mm square and thickness is 360 microns. The scheme of cross section of 3D SiP is shown in Fig. 2. Four Si chips were stacked in 3D SiP. Si chip Si interposer TSV SiO 2 Resin Fig.1. Cross-section of 3D stacked stru...