The improvement of atomic layer deposited SiO2/4H-SiC interfaces via a high temperature forming gas anneal

Renz, Arne Benjamin; Vavasour, Oliver J.; Gammon, P. M.; Li, Fan; Dai, Tianxiang; Antoniou, Marina; Baker, Guy; Bashar, Erfan; Grant, Nicholas E.; Murphy, John D.; Mawby, P.A.; Shah, V. A.

doi:10.1016/j.mssp.2020.105527

Cited by 15 publications

(13 citation statements)

References 21 publications

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“…The concentration of Si and O dangling bonds in the SiO 2 substrate was reduced under H + -ion-rich growth conditions during atomic layer deposition. 28 Therefore, the passivation of SiO 2 by H + injection is consistent with the previous observations.…”

supporting

confidence: 91%

“…However, proton injection using gate bias can passivate dangling bonds in the SiO 2 layer, transforming it into an h-BN-like substrate, as demonstrated in Figures a and b. The concentration of Si and O dangling bonds in the SiO 2 substrate was reduced under H + -ion-rich growth conditions during atomic layer deposition . Therefore, the passivation of SiO 2 by H + injection is consistent with the previous observations.…”

supporting

confidence: 87%

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One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device

Ahn,

Kim,

Kim

et al. 2023

Nano Lett.

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supporting

confidence: 91%

supporting

confidence: 87%

One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device

Ahn,

Kim,

Kim

et al. 2023

Nano Lett.

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“…This result is consistent with the results reported by other research groups. [34][35][36][37] However, as can be seen in this figure, in the accumulation condition, the density of the ITs is 015503-4 © 2024 The Japan Society of Applied Physics smaller than the values calculated by other methods. Nevertheless, in the full-distributed circuit model, the ITs are considered to be located inside the SiC layer and do not participate in the electron exchange process with the oxide layer.…”

Section: Resultsmentioning

confidence: 55%

Study of interface-trap and near-interface-state distribution in a 4H-SiC MOS capacitor with the full-distributed circuit model

Van Cuong,

Koyanagi,

Meguro

et al. 2024

Jpn. J. Appl. Phys.

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In this research, by applying the full-distributed circuit model, the contribution of interface traps and near-interface states on electrical characteristics of 4H-SiC MOS capacitor were classified in a wide range of operation. By fitting the measured capacitance and conductance at a certain value of applied gate voltage when the frequency varied from 1 kHz to 1 MHz, the density of both near interface state and interface trap were determined. The results reveal that, at room temperature, the frequency dispersion of the capacitance in depletion condition is mainly caused by the contribution of interface traps. Nevertheless, in strong accumulation condition, near-interface states become dominant for the frequency dispersion of the capacitance. Furthermore, the full-distributed circuit model also successfully explained the electrical characteristics of the 4H-SiC MOS capacitor when operating at 500℃.

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“…Oxides formed using ALD and thermal oxidation were considered. A FG postdeposition anneal was carried out on ALD-deposited samples since this process has recently shown a big improvement in terms of electrical parameters and interface quality when compared to as-deposited ALD silicon dioxide and thermal oxide [16,17].…”

Section: Electrical Resultsmentioning

confidence: 99%

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

Renz

Vavasour

et al. 2021

Semicond. Sci. Technol.

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This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 µm width and 450 nm depth) with a density of 1.09 × 10 5 cm −2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C-V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3 × 10 11 cm −2 eV −1 at E C −E T = 0.2 eV. The homo-epitaxially grown 3C-SiC material's suitability for MOS applications could also be confirmed by leakage current measurements.

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The improvement of atomic layer deposited SiO2/4H-SiC interfaces via a high temperature forming gas anneal

Cited by 15 publications

References 21 publications

One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device

One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device

Study of interface-trap and near-interface-state distribution in a 4H-SiC MOS capacitor with the full-distributed circuit model

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

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The improvement of atomic layer deposited SiO2/4H-SiC interfaces via a high temperature forming gas anneal

Cited by 15 publications

References 21 publications

One-Step Passivation of Both Sulfur Vacancies and SiO2 Interface Traps of MoS2 Device

One-Step Passivation of Both Sulfur Vacancies and SiO2 Interface Traps of MoS2 Device

Study of interface-trap and near-interface-state distribution in a 4H-SiC MOS capacitor with the full-distributed circuit model

Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications

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Product

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One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device

One-Step Passivation of Both Sulfur Vacancies and SiO₂ Interface Traps of MoS₂ Device