The impact and implication of BTI/HCI decoupling on ring oscillator

Hsieh, Min-Hsiu; Huang, Yu-Jen; Yew, T.-Y.; Wang, W.; Lee, Y.-H.

doi:10.1109/irps.2015.7112758

Cited by 15 publications

(8 citation statements)

References 12 publications

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“…4, the FITs, determined by the slopes, are plotted against frequency in two different experiments. The data demonstrates the clear advantage of RO generated frequencies in a single chip [15]. In the examples of Fig.…”

Section: Ea and γ Extrapolationmentioning

confidence: 55%

Reliability prediction with MTOL

Bernstein¹,

Bensoussan²,

Bender³

2017

Microelectronics Reliability

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Here, we develop a comprehensive reliability prediction of FPGA devices from data motivated by physics of failure. The Multiple Temperature Operational Life (MTOL) testing method was used to calculate the failure in time (FIT) of 3 different mechanisms on both 45 nm and 28 nm technologies. We confirmed that there is significant hot carrier injection (HCI) at sub-zero temperatures in 45 nm technology. Surprisingly, we found that 28 nm exhibits no HCI degradation even with up to 1.6 V on the core. As a result, we show that there is no effect of frequency on the reliability. This means that at 28 nm and possibly smaller technologies, the devices can be de-rated or up-rated based only on the NBTI model and therefore reliability is dependent only on operating Voltage and Temperature with a single activation energy. Notably, the activation energies and voltage acceleration factors for both technologies are remarkably similar. This demonstration shows that, unlike other conventional qualification procedures, the MTOL testing procedure gives a broad description of the reliability from sub-zero to high temperatures. This procedure provides FIT prediction which can be applied to newer technologies, specifically 20 nm and 16 nm and beyond.

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Section: Ea and γ Extrapolationmentioning

confidence: 55%

Reliability prediction with MTOL

Bernstein¹,

Bensoussan²,

Bender³

2017

Microelectronics Reliability

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show abstract

“…The design would draw approximately 420 mW of static power, as estimated using the Power Analyzer Tool (available in Quartus). Comparing RO-PUFs, this study did not classify or identify the impact of aging, which may shift the frequency [53][54][55]. For instance, a high-temperature setup and its duration for extracting data from chips may degrade the frequency-this work extracts a frequency at a temperature no higher than 50 • C. In general, the result of this work is better compared to the previously proposed methods using a similar platform (Altera), and the performance is as good as the latest works implemented onto Xilinx [51,52].…”

Section: Results Comparisonsmentioning

confidence: 97%

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

et al. 2021

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The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

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“…The idea was realized on a 28 nm Xilinx chip with the help of 90 nm Spartan 3 for extracting reliability upon voltage variation. Upon comparing RO-PUFs, this study did not classify or identify the aging impact that may shift the frequency [42][43][44]. For instance,…”

Section: Authormentioning

confidence: 99%

Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing

et al. 2021

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The main issue of ring oscillator physical unclonable functions (RO-PUF) is the existence of unstable ROs in response to environmental variations. The RO pairs with close frequency differences tend to contribute bit flips, reducing the reliability. Research on improving reliability has been carried out over the years. However, it has led to other issues, such as decreasing the uniqueness and increasing the area utilized. Therefore, this paper proposes a uniform RO-PUF, requiring a smaller area than a conventional design, aiming to balance reliability and uniqueness. We analyzed RO runtimes to increase reliability. In general, our method (uniqueness = 47.48%, reliability = 99.16%) performs better than previously proposed methods for a similar platform (Altera), and the reliability is as good as the latest methods using the same IC technology (28 nm). Moreover, the reliability is higher than that of RO-PUF with challenge and response pair (CRP) enhancements. The evaluation was performed in longer runtimes, where the pulses produced by ROs exceeded the counter capacity. This work recommends choosing ranges of the runtime of RO for better performance. For the 11-stage ROs, the range should be 1.598–4.30 ms, or 6.12–8.61 ms, or 12.24–12.91 ms. Meanwhile, for the 20-stage, the range should be 2.717–8.37 ms, or 10.97–16.74 ms, or 21.93–25.10 ms.

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The impact and implication of BTI/HCI decoupling on ring oscillator

Cited by 15 publications

References 12 publications

Reliability prediction with MTOL

Reliability prediction with MTOL

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing

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