The<i>Programmable Logic-in-Memory</i>(PLiM) Computer

Gaillardon, Pierre-Emmanuel; Amarù, Luca; Siemon, Anne; Linn, Eike; Waser, Rainer; Chattopadhyay, Anupam; Micheli, Giovanni De

doi:10.3850/9783981537079_0970

Cited by 78 publications

(60 citation statements)

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“…So far a variety of approaches has been proposed for synthesis of logic-in-memory computing circuits, mostly based on material implication (IMP: p → q =p ∨ q) [12], [13] and some using other basic operations [14], [15], [11]. In all these approaches, the target function can only be executed using a certain number of RRAM devices and after a number of operations, which increases rapidly as the size of the function increases.…”

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

“…In [11], an operation based on the 3-input majority function xyz = xy ∨ xz ∨ yz = (x ∨ y)(x ∨ z)(x ∨ z) was proposed to perform Boolean functions on a crossbar array of Bipolar Resistive Switches (BRS). The operation called 3-input Resistive Majority (RM 3 ) exploits an intrinsic majority property of resistive memories.…”

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

“…When the controller is on, the circuit starts performing computation. The controller consists of a simple finite state machine and few work registers, in order to operate the RM 3 instruction [11]. The instruction format consists of the first operand A, the second operand B and the destination Z. Operands A and B are then read from constants or from the memory array, and RM 3 is performed during the write operation to the memory location Z by setting P to A and Q to B.…”

Section: Case Study: Endurance-aware Compilationmentioning

confidence: 99%

“…To execute a Boolean function, PLiM translates its MIG representation to a set of RM 3 instructions. Implementing logic operations within memory cells requires to control the distribution of signals and the scheduling of operations considering latency, area, and management [11], [21].…”

Section: Case Study: Endurance-aware Compilationmentioning

confidence: 99%

“…We target the Programmable Logic-inMemory (PLiM) computer architecture proposed in [11] as a case study. We survey the reasons of unbalanced write traffic in PLiM and propose an endurance management scheme for it to get a more uniform distribution of the writes over all memory cells.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

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Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Section: Case Study: Endurance-aware Compilationmentioning

confidence: 99%

Section: Case Study: Endurance-aware Compilationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

Self Cite

View full text Add to dashboard Cite

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Complementary Lateral‐Spin–Orbit Building Blocks for Programmable Logic and In‐Memory Computing

Zhang

Cao

et al. 2020

Adv Elect Materials

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Current-driven switching of nonvolatile spintronic materials and devices based on spin-orbit torques offer fast data processing speed, low power consumption, and unlimited endurance for future information processing applications. Analogous to conventional CMOS technology, it is important to develop a pair of complementary spin-orbit devices with differentiated magnetization switching senses as elementary building blocks for realizing sophisticated logic functionalities.Various attempts using external magnetic field or complicated stack/circuit designs have been proposed, however, plainer and more feasible approaches are still strongly desired. Here we show that a pair of two locally laser annealed perpendicular Pt/Co/Pt devices with opposite laser track configurations and thereby inverse field-free lateral spin-orbit torques (LSOTs) induced switching senses can be adopted as such complementary spin-orbit building blocks. By electrically programming the initial magnetization states (spin down/up) of each sample, four Boolean logic gates of AND, OR, NAND and NOR, as well as a spin-orbit half adder containing an XOR gate, were obtained. Moreover, various initialization-free, working current intensity-programmable stateful logic operations, including material implication (IMP) gate, were also demonstrated by regarding the magnetization state as a logic input. Our complementary LSOT building blocks provide a potentially applicable way towards future efficient spin logics and in-memory computing architectures.

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Memristive Devices for New Computing Paradigms

Kim

Jang

2020

Advanced Intelligent Systems

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Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

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TheProgrammable Logic-in-Memory(PLiM) Computer

Cited by 78 publications

References 0 publications

Endurance management for resistive Logic-In-Memory computing architectures

Endurance management for resistive Logic-In-Memory computing architectures

Complementary Lateral‐Spin–Orbit Building Blocks for Programmable Logic and In‐Memory Computing

Memristive Devices for New Computing Paradigms

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