The hierarchical timing pair model

Chandrachoodan, Nitin; Bhattacharyya, Shuvra S.; Liu, K. J. Ray

doi:10.1109/iscas.2001.922061

Cited by 2 publications

(4 citation statements)

References 8 publications

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“…This was evaluated (Table 5) by profiling the scheduling routines applied on design D1 from Table 4. The first column corresponds to conventional scheduling, the second column represents the scheduling time for the proposed slack-based approach, while the third column provides the scheduling time for the proposed approach when timing analysis is done using the Bellman-Ford algorithm as in [10]. Based on our experience with customers using our technology, we observe that 20% performance degradation is acceptable for a user, while the formulation based on the Bellman-Ford algorithm is impractical (see comments in Section III).…”

Section: Resultsmentioning

confidence: 99%

“…Finally, in [10], a hierarchical timing model was suggested for modules used in HLS. This model captures both combinational and sequential aspects of module behaviors.…”

Section: Prior Workmentioning

confidence: 99%

“…It reduced timing analysis to applying the Bellman-Ford algorithm to the timing constraint graph, which is more efficient than the method in [8], but is still costly for practical applications (see experimental results). Another limitation of the approach in [10] is that it cannot model the mobility of operations within several clock cycles.…”

Section: Prior Workmentioning

confidence: 99%

See 2 more Smart Citations

Exploiting area/delay tradeoffs in high-level synthesis

Kondratyev¹,

Lavagno²,

Meyer³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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− This paper proposes an enhanced scheduling approach for high-level synthesis, which relies on a multi-cycle behavioral timing analysis step that is performed before and during scheduling. The goal of this analysis is to accurately evaluate the criticality of operations and determine the most suitable candidate resources to implement them. The efficiency of the approach is confirmed by testing it on industrial examples, where it achieves, on average, 9% area savings after logic synthesis. I.

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Section: Resultsmentioning

confidence: 99%

“…Finally, in [10], a hierarchical timing model was suggested for modules used in HLS. This model captures both combinational and sequential aspects of module behaviors.…”

Section: Prior Workmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting area/delay tradeoffs in high-level synthesis

Kondratyev¹,

Lavagno²,

Meyer³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…Preliminary versions of the results in this paper were published in [9] and [10] for the timing pair model and its extension to multirate systems, respectively. …”

mentioning

confidence: 99%

The hierarchical timing pair model for multirate DSP applications

Chandrachoodan

Bhattacharyya

Liu

2004

IEEE Trans. Signal Process.

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Abstract-The problem of representing timing information associated with functions in a dataflow graph is considered. This information is used for constraint analysis during behavioral synthesis of appropriate architectures for implementing the graph. Conventional models for timing suffer from shortcomings that make it difficult to represent timing information in a hierarchical manner for sequential and multirate systems. Some of these shortcomings are identified, and an alternate timing model that does not have these problems for hardware implementations is provided.We introduce the concept of timing pairs to model delay elements in sequential and multirate circuits and show how this allows us to derive hierarchical timing information for complex circuits. The resulting compact representation of the timing information can be used to streamline system performance analysis. In addition, several analytical results that previously applied only to single rate systems can now be extended to multirate systems.We present an algorithm to compute the timing parameters and have used this to compute timing parameters for a number of benchmark circuits. The results obtained on several ISCAS benchmark circuits as well as several multirate dataflow graphs corresponding to useful signal processing applications are presented. These results show that the new representation model can result in large reductions in the amount of information required to represent timing for hierarchical systems.

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The hierarchical timing pair model

Cited by 2 publications

References 8 publications

Exploiting area/delay tradeoffs in high-level synthesis

Exploiting area/delay tradeoffs in high-level synthesis

The hierarchical timing pair model for multirate DSP applications

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