The hierarchical timing pair model for multirate DSP applications

Chandrachoodan, Nitin; Bhattacharyya, Shuvra S.; Liu, K.J.R.

doi:10.1109/tsp.2004.826178

Cited by 4 publications

(6 citation statements)

References 19 publications

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“…Chandrachoodan et al provide a method for a hierarchical view of Homogeneous Synchronous Data-Flow (HSDF) graphs for Digital Signal Processor (DSP) applications [3]. The new hierarchical node (block) has a delay of the worst case of all the paths from input to output inside.…”

Section: Temporal Models For Hardware Designmentioning

confidence: 99%

“…6a). There are a couple of different permutations possible on the patterns that would result in a feasible architecture, those permutations are [1, 1, 1, 1, 1, 1], [2, 2, 2], [3,3]. These are the divisors of the original pattern.…”

Section: The Basic Idea Of Combining Sdf-ap With a Functional Languagementioning

confidence: 99%

“…If A is in the third phase, then B can start if there are 3 or more elements in the FIFO because A will produce 1 element in this third phase. So the list that keeps track of the minimum number of elements required in the FIFO before a node can fire according to that edge is[2,2,3] in this example. Algorithm 1 calculates such a list for a given production and consumption pattern.…”

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confidence: 99%

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Folmer

Groote

Bekooij

2022

Lecture Notes in Computer Science

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Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns.Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog.Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption.The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLStool.

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Section: Temporal Models For Hardware Designmentioning

confidence: 99%

Section: The Basic Idea Of Combining Sdf-ap With a Functional Languagementioning

confidence: 99%

mentioning

confidence: 99%

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Folmer

Groote

Bekooij

2022

Lecture Notes in Computer Science

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“…A large body of research exists on synthesizing hardware from dataflow models [1,5,10,13,14,15,19,35,37]. These works study problems similar to the glue design problem, however, some of them assume that hardware components for actors are to be synthesized, or at least that they have certain characteristics that match the proposed synthesis techniques.…”

Section: Related Workmentioning

confidence: 99%

Correct and non-defensive glue design using abstract models

Tripakis

Andrade

Ghosal

et al. 2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Current hardware design practice often relies on integration of components, some of which may be IP or legacy blocks. While integration eases design by allowing modularization and component reuse, it is still done in a mostly ad hoc manner. Designers work with descriptions of components that are either informal or incomplete (e.g., documents in English, structural but non-behavioral specifications in IP-XACT) or too low-level (e.g., HDL code), and have little to no automatic support for stitching the components together. Providing such support is the glue design problem.This paper addresses this problem using a model-based approach. The key idea is to use high-level models, such as dataflow graphs, that enable efficient automated analysis. The analysis can be used to derive performance properties of the system (e.g., component compatibility, throughput, etc.), optimize resource usage (e.g., buffer sizes), and even synthesize low-level code (e.g., control logic). However, these models are only abstractions of the real system, and often omit critical information. As a result, the analysis outcomes may be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). The paper examines these situations and proposes a correct and nondefensive design methodology that employs the right models to explore accurate performance and resource trade-offs.

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“…One noticeable difference is that our model supports memory actors that share data. Hierarchical dataflow models have also been proposed before to model multi-rate DSP applications with constraints [4].…”

Section: Related Workmentioning

confidence: 99%

A parameterized dataflow language extension for embedded streaming systems

Lin

Choi

Mahlke

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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Abstract-Many embedded DSP systems can be characterized as streaming applications. Imperative programming languages are ill suited for describing the concurrency within these DSP systems. SPEX is a language extension designed to let the programmers describe the inherent parallelism within DSP systems. In this paper, we highlight SPEX's language features for describing the streaming computation and communication patterns of DSP systems, and allowing the compiler to generate efficient code for embedded DSP architectures. This language extension is based on the parameterized dataflow computation model, with modifications to better describe DSP systems' complex streaming patterns. SPEX is applied as an extension onto the C++ programming language. It consists of a set of language constructs for describing the semantics of parameterized dataflow computations, and a set of language restrictions for helping the embedded compilation process. In this paper, the W-CDMA wireless protocol is used as our case study.

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The hierarchical timing pair model for multirate DSP applications

Cited by 4 publications

References 19 publications

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Correct and non-defensive glue design using abstract models

A parameterized dataflow language extension for embedded streaming systems

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