High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Folmer, H.H.; Groote, Robert de; Bekooij, Marco

doi:10.1007/978-3-031-15074-6_1

Cited by 3 publications

(2 citation statements)

References 31 publications

(47 reference statements)

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“…SDF-AP too does not match perfectly with FPGA implementations and has been refined to handle stalls and direct token consumption [13], still facing the same complexity and poor scalability. SDF-AP has also been used in the generation of HLS code from templated Haskell [15]; this work is limited by the access patterns required as an input from the user. In any case, it is difficult to know the exact access patterns, especially for closed-source implementations (IP).…”

Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

Honorat,

Dardaillon,

Miomandre

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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High-Level Synthesis (HLS) tools are mature enough to provide efficient code generation for computation kernels on FPGA hardware. For more complex applications, multiple kernels may be connected by a dataflow graph. Although some tools, such as Xilinx Vitis HLS, support dataflow directives, they lack efficient analysis methods to compute the buffer sizes between kernels in a dataflow graph. This paper proposes an original method to safely approximate such buffer sizes. The first contribution computes an initial overestimation of buffer sizes, wihout knowing the memory access patterns of kernels. The second contribution iteratively refines those buffer sizes thanks to cosimulation. Moreover, the paper introduces an open source framework using these methods to facilitate dataflow programming on FPGA using HLS. The proposed methods and framework have been tested on 7 dataflow applications, and outperform Vitis HLS cosimulation in 5 benchmarks, either in terms of BRAM and LUT usage, or in term of exploration time. In the 2 other benchmarks, our best method gets results similar to Vitis HLS. Last but not least, our method admits directed cycles in the application graphs.

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Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

Honorat,

Dardaillon,

Miomandre

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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“…Blanchette et al (2022) use TH to simplify the development of Liquid Haskell proofs. Folmer et al (2022) used TH to synthesize CλaSH (Baaij, 2015) ASTs to be processed. In similar fashion, Materzok (2022) used TH to translate YieldFSM programs to CλaSH.…”

Section: Generating Extra Codementioning

confidence: 99%

Orchestrating the Internet of Things with Task-Oriented Programming

Lubbers

2023

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The development of reliable software for the internet of things (IoT) is difficult because IoT systems are dynamic, interactive, distributed, collaborative, multi-tiered, and multitasking in nature. The complexity is increased further by semantic friction that arises through different hardware and software characteristics between tiers. Many computers that operate in IoT systems are edge devices that interact with the environment using sensors and actuators. Edge devices are often powered by low-cost microcontrollers designed for embedded applications. They have little memory, unhurried processors, and are slow in communication but are also small and energy efficient. Task-oriented programming (TOP) can cope with the challenges of IoT programming. In TOP, the main building blocks are tasks, an abstract representation of work. During execution, the current value of the task is observable, and other tasks can act upon it. Collaboration patterns can be modelled by combining and transforming tasks into compound tasks. Programming edge devices benefits from TOP as well, but running such a system within the limitations of resource-constrained microcontrollers is not straightforward. This dissertation demonstrates how to include edge devices in TOP systems using domain-specific languages (DSLs). With these techniques, all tiers and their interoperation of an IoT system are specified in a single high-level source, language, paradigm, high abstraction level, and type system. First, I present advanced DSL embedding techniques. Then mTask is shown, a TOP DSL for IoT edge devices, embedded in iTask. Tasks are constructed and compiled at run time in order to allow tasks to be tailored to the current work requirements. The task is then sent to the device for interpretation. A device is programmed once with a lightweight domain-specific OS to be used in an mTask system. This OS executes tasks in an energy-efficient way and automates all communications and data sharing. All aspects of the mTask system are shown: example applications, language design, implementation details, integration with iTask, and green computing facilities such as automatic sleeping. Finally, tierless IoT programming is compared to traditional tiered programming. In tierless programming frameworks, the size of the code and the number of required programming languages is reduced significantly. By using a single paradigm and a system-wide type system, tierless programming reduces problems such as semantic friction; maintainability and robustness issues; and interoperation safety.

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