Exploiting area/delay tradeoffs in high-level synthesis

Kondratyev,; Lavagno,; Meyer,; Watanabe, Toru

doi:10.1109/date.2012.6176646

Cited by 4 publications

(3 citation statements)

References 12 publications

(15 reference statements)

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“…Siret et al use CAL in their HLS two-step approach in which they compile dataflow programs into hardware while keeping as many similarities as possible from the source and then letting the synthesis tool perform optimizations [28]. Kondratyev et al propose an HLS scheduling approach in which they split the SystemC input specification into a Control Flow Graph (CFG) and a Data Flow Graph (DFG) [16]. The CFG is constructed using conditionals, loops, and waits in the input specification.…”

Section: Temporal Models For Hardware Designmentioning

confidence: 99%

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Folmer

Groote

Bekooij

2022

Lecture Notes in Computer Science

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Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns.Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog.Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption.The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLStool.

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Section: Temporal Models For Hardware Designmentioning

confidence: 99%

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

Folmer

Groote

Bekooij

2022

Lecture Notes in Computer Science

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“…There are several approaches for library characterization. The first approach performs a rapid logic synthesis during the scheduling and binding of the operations to determine the most suitable candidate resources, like in Cadence's C-to-Silicon [57]. However, this approach has a high cost in terms of computation time, especially when the HLS is repeatedly performed for the same target.…”

Section: E Hardware Resource Librarymentioning

confidence: 99%

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Nane

Sima

Pilato

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

436

182

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Abstract-High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing FPGA circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and use of resources.

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“…The distinctive characteristics of the proposed hardware binding algorithm is that it can be executed sequentially after scheduling. Thus it avoids the iterative scheduling and binding strategy proposed in works like [190] and is hence puts a smaller demand on run time compared to other iterative approaches [190].…”

Section: Joint Area-delay Optimized Hardware Binding Algorithmmentioning

confidence: 99%

Intelligent high level synthesis for customization on reconfigurable platforms

Sinha¹

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High level synthesis (HLS) using C/C++ has increasingly become a critical step in the realization of complex digital systems. One of the major research focus areas in this space has been to realize efficient synthesis of complex systems without violating stringent time-to-market constraints. Most of the related work cited in the literature has been mainly xi 6.2 Matrix size determination for matrix-matrix multiplication.

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Exploiting area/delay tradeoffs in high-level synthesis

Cited by 4 publications

References 12 publications

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Intelligent high level synthesis for customization on reconfigurable platforms

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